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W5300 Datasheet(PDF) 55 Page - WIZnet Co., Ltd |
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W5300 Datasheet(HTML) 55 Page - WIZnet Co., Ltd |
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55 / 128 page ![]() © Copyright 2008-2014 WIZnet Co.,Ltd. All rights reserved. 55 each interrupt bit of IR. When any bit of IR is set as ‘1’ and its corresponding bit of IMR is also set as ‘1’, interrupt is issued to the host. (‘/INT’ pin is asserted from high to low). If corresponding IMR bit is not set as ‘0’, the interrupt is not issued to the host (‘INT’ pin keeps high) even t hough IR bit is set as ‘1’. IMR0 15 14 13 12 11 10 9 8 0x08004 IPCF DPUR PPPT FMTU - - - - 0x004 0 0 0 0 0 0 0 0 IMR1 7 6 5 4 3 2 1 0 0x08005 S7_INT S6_INT S5_INT S4_INT S3_INT S2_INT S1_INT S0_INT 0x005 0 0 0 0 0 0 0 0 IMR(15:8)/IMR0(7:0) Bit Symbol Description 15 IPCF IR(IPCF) Interrupt Mask 14 DPUR IR(DPUR) Interrupt Mask 13 PPPT IR(PPPT) Interrupt Mask 12 FMTU IR(FMTU) Interrupt Mask 11 - Reserved 10 - Reserved 9 - Reserved 8 - Reserved IMR(7:0)/IMR1(7:0) Bit Symbol Description 7 S7_INT IR(S7_INT) Interrupt Mask 6 S6_INT IR(S6_INT) Interrupt Mask 5 S5_INT IR(S5_INT) Interrupt Mask 4 S4_INT IR(S4_INT) Interrupt Mask 3 S3_INT IR(S3_INT) Interrupt Mask 2 S2_INT IR(S2_INT) Interrupt Mask 1 S1_INT IR(S1_INT) Interrupt Mask 0 S0_INT IR(S0_INT) Interrupt Mask |
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