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4.2 Indirect Mode Registers

In case of MR(IND) = ‘1’, W5300 operates as indirect address mode. Target host system can

access indirectly COMMON and SOCKET registers using only MR, IDM_AR, IDM_DR(That is,

Target host system can access directly MR, IDM_AR, IDM_DR which are only mapped in T.M.S).

IDM_AR(Indirect Mode Address Register) [R/W] [0x08002/----][0x0000]

It sets an address offset of COMMON registers or SOCKET registers that are indirectly

accessible. IDM_AR(0) or IDM_AR1(0) which is the least significant bit of IDM_AR, are ignored.

Ex) Accessing S4_RX_FIFOR(0x330) is as below.

IDM_AR0 = MSB (0x03) of address offset of S4_RX_FIFOR

IDM_AR1 = LSB (0x30) of address offset of S4_RX_FIFOR

IDM_AR(0x08002/----)

IDM_AR0(0x08002/----)

IDM_AR1(0x08003/----)

0x03

0x30

IDM_DR(Indirect Mode Data Register) [R/W] [0x08004/----][0x0000]

It accesses a real data value of COMMON or SOCKET registers that are indirectly accessible.

IDM_DR0 corresponds to MSB values of the register addressed by IDM_AR, and IDM_DR1

does to LSB value of that.

When using 8bit data bus width and accessing LSB of any register, IDM_DR1 should be

accessed. When accessing MSB, IDM_DR0 should be accessed.

It accesses the real value of COMMON or SOCKET registers which have the address offset in

IDM_AR.

The MSB and LSB value of register addressed by IDM_AR corresponds to DM_DR0 and

IDM_DR1 respectively.

At 8 bit data bus width, if the host access the LSB value of register addressed by IDM_AR then

use IDM_DR1, and if the host access the MSB value of that then use IDM_DR0.

Ex1) When the host writes IR(0x002) with the value 0x80F0,

16 Bit Data Bus Width ( MR(DBW) = ‘1’)

8 Bit Data Bus Width ( MR(DBW) = ‘0’)

IDM_AR = 0x0002

IDM_DR = 0x80F0

IDM_AR0 = 0x00

IDM_AR1 = 0x02

IDM_DR0 = 0x80

IDM_DR1 = 0xF0

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