AM625 datasheet(113/235 Pages) TI

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determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO =

0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -

(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF

7.10.4.1.1.2 Shunt Capacitance

The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for

MCU_OSC0 operating conditions defined in Table 7-17. Shunt capacitance, Cshunt, of the crystal circuit is a

combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal

circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB

designer should be able to extract mutual parasitic capacitance between these signal traces. The device

package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined

in Table 7-18.

PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is

typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can

also be minimized by placing a ground trace between these signals when the layout requires them to be routed

in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as

possible when selecting a crystal.

AM65x_MCU_OSC_SC_06

Device

MCU_OSC0_XO

MCU_OSC0_XI

PCBXIXO

PCB

Signal Traces

Crystal Circuit

Components

XIXO

Figure 7-19. Shunt Capacitance

A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt

capacitance specified by the crystal manufacturer.

Cshunt ≥ CO + CPCBXIXO + CXIXO

For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,

CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.

7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source

Figure 7-20 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8-V

LVCMOS square-wave digital clock source.

Note

A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up. This

is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that may enter a

unknown state when DC is applied to the input. Therefore, application software should power down

MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states.

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AM625, AM623

SPRSP58 – JUNE 2022

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