LT4293 datasheet(31/44 Pages) AD

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LTC9101-2/LTC9102

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Code Download

LTC9101-2 firmware is field-upgradable by downloading

and executing firmware images.

Contact Analog Devices for code download procedures

and firmware images.

Firmware images are stored in a dedicated flash partition.

A fully-compliant IEEE 802.3bt firmware image is pre-

configured on the LTC9101-2. The firmware image may

be overwritten by the user.

Two complete copies of the firmware image are main-

tained under separate ECC and CRC protection for maxi-

mum data protection.

Stored Configurations

Custom I2C register map initial values may optionally be

stored in a dedicated flash partition (configuration pack-

age). When shipped from the factory, the LTC9101-2

contains a default configuration package where register

map initial values are as specified in the LTC9101-2NDASI

Software Interface. Register map default configurations

may be stored during manufacturing bring up or field-

updated via configuration package download and will be

auto-loaded at boot.

Contact ADI applications support for assistance in gener-

ating custom configuration packages. Configuration pack-

ages are downloaded using normal code download mech-

anisms. Package headers ensure configuration packages

are identified and stored in the appropriate flash partition.

If a stored configuration is utilized, the state of the

PWRMD[1:0] pins can be overwritten by a configura-

tion package. CFG[1:0] are still required to inform the

LTC9101-2 how many LTC9102s are attached. AD[4:1]

are still required to inform the LTC9101-2 of the base I2C

chip address.

Two identical copies of the configuration image are main-

tained under separate ECC and CRC protection for maxi-

mum data protection.

In 3-bit priority mode, e.g., Multibit Priority is enabled,

each port can be configured to one of eight Multibit Power

Priorities. When the host system wants certain group of pri-

ority ports to be shut down, it will send the matching shut-

down code on the OSS pin. The LTC9101-2 compares the

shutdown code received on OSS with the Multibit Power

Priority of each port and shuts down ports which are less

than or equal to the flagged shutdown code (see Figure 25).

If a port is turned off via OSS, the corresponding Detection

and Classification Enable bits remain enabled, so the port

will begin redetection.

Port Remapping

The LTC9101-2/LTC9102 supports the ability to remap

ports logically. This can be achieved by writing the appro-

priate values into the port remapping register to achieve

the remapping (see Table 16). By default, there is no

remapping.

Table 16. Port Remapping

CODE

REMAPPING

00b

Port 1

01b

Port 2

10b

Port 3

11b

Port 4

Physical port remapping is unlimited; any physical port

can be mapped to any logical port. When the ports are

configured for 4P operation, the 4P mapping is always

logical port 1 and port 2 for one 4P port and logical port

3 and port 4 for the other 4P port. Physical port mapping

can map any two of the physical 2P ports to the logical 4P

port: Logical port 1,2 can map to physical port 1,2; 1,3;

1,4; 2,1; 2,3; 2,4; 3,1; 3,2; 3,4; 4,1; 4,2; or 4,3.

9101-2 F25

IDLE

OSS

GATE

3.3V

IDLE

SC2

SC1

SC0

START BITS

SHUTDOWN CODE

tOSS_OFF

tBIT

tOSS

tr_OSS

tf_OSS

Figure 25. Multi Bit Priority Port Shutdown of Lower-Priority Port

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