LTC9101-2/LTC9102

6

Rev. 0

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ELECTRICAL CHARACTERISTICS The

l

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted.

(Notes 3 and 4)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifespan.

Note 2: This chipset includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 140°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 3: All currents into device pins are positive; all currents out of device

pins are negative.

Note 4: The LTC9102 operates with a negative supply voltage (with

respect to AGND). To avoid confusion, voltages in this data sheet are

referred to in terms of absolute magnitude.

Note 5: tDIS is the same as tMPDO defined by IEEE 802.3.

Note 6: The LTC9101-2 digital interface operates with respect to DGND. All

logic levels are measured with respect to DGND.

Note 7: Guaranteed by design, not subject to test.

Note 8: The IEEE 802.3 defines MPS as the set of minimum PSE and PD

input current requirements to maintain power. An LTC9101-2/LTC9102

port resets its MPS timer when VSENSEn – VSSKn ≥ VHOLD-2P for tMPS

and removes port power when VSENSEn – VSSKn ≥ VHOLD-2P for a period

longer than tDIS. See Disconnect section.

Note 9: Values Measured at VIHD.

Note 10: If a fault condition occurs during an I2C transaction, the INT pin

will not be pulled down until a stop condition is present on the I2C bus.

Note 11: Load characteristics of the LTC9102 during Mark: 7V < (AGND –

VOUTn) < 10V.

Note 12: See the LTC9101-2NDASI Software Programming documentation

for information on serial bus usage and device configuration and

status registers.

Note 13: Do not source or sink current from CAP1, CAP2, CAP3 and CAP4.

Note 14: For single-signature PDs, tPON is measured from end of valid

detect on either power channel. For dual-signature PDs, tPON is measured

from the end of valid detect on the same power channel.

Note 15: Port current and port power measurements depend on sense

resistor value (0.1Ω typical). See External Component Selection for details.

Note 16: See Inrush Control for details on inrush threshold selection.

Note 17: ADC characteristics and typical performance are described in

terms of LTC9102 hardware capability. Measurements from LTC9102

are processed and synthesized by the LTC9101-2. See LTC9101-2NDASI

Software Interface for register descriptions and LSB weights, as

presented to the user (port current, port voltage, VEE voltage, and system

temperature).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I2C Watchdog Timer Duration

l

1.5

2

3

s

Minimum Pulse Width for Masked Shutdown

l

3

µs

Minimum Pulse Width for RESET

l

4.5

µs

I2C Timing (Note 7)

fSCLK

Clock Frequency

l

1

MHz

t1

Bus Free Time

Figure 5 (Note 9)

l

480

ns

t2

Start Hold Time

Figure 5 (Note 9)

l

240

ns

t3

SCL Low Time

Figure 5 (Note 9)

l

480

ns

t4

SCL High Time

Figure 5 (Note 9)

l

240

ns

t5

SDAIN Data Hold Time

Figure 5 (Note 9)

l

60

ns

Data Clock to SDAOUT Valid

Figure 5 (Note 9)

l

250

ns

t6

Data Set-Up Time

Figure 5 (Note 9)

l

80

ns

t7

Start Set-Up Time

Figure 5 (Note 9)

l

240

ns

t8

Stop Set-Up Time

Figure 5 (Note 9)

l

240

ns

tr

SCL, SDAIN Rise Time

Figure 5 (Note 9)

l

120

ns

tf

SCL, SDAIN Fall Time

Figure 5 (Note 9)

l

60

ns

Fault Present to INT Pin Low

(Notes 9, 10)

l

150

ns

Stop Condition to INT Pin Low

(Notes 9, 10)

l

1.5

µs

ARA to INT Pin High Time

(Note 9)

l

1.5

µs

SCL Fall to ACK Low

(Note 9)

l

250

ns