LT4293 datasheet(13/44 Pages) AD

13 / 44 page

LTC9101-2/LTC9102

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

LTC9101-2

CFG[1:0] (Pins 2, 1 Respectively): Device Configuration

Inputs. Tie the configuration pins high or low to set num-

ber of ports, channels per port, and number of connected

LTC9102s. See Device Configuration for details. CFG[0] is

ignored when a custom configuration package is present.

See Stored Configurations for details.

CAP[2:1] (Pins 7, 23 Respectively): Core Power Supply

Bypass Capacitors. Connect each pin to a 1μF capacitance to

DGND for the internal 1.2V regulator bypass. Do not use other

capacitor values. Do not source or sink current from this pin.

CPD (Pin 8): Clock Transceiver Positive Input Output

(Digital). Connect to CPA through a data transformer.

CND (Pin 9): Clock Transceiver Negative Input Output

(Digital). Connect to CNA through a data transformer.

DPD (Pin 10): Data Transceiver Positive Input Output

(Digital). Connect to DPA through a data transformer.

DND (Pin 11): Data Transceiver Negative Input Output

(Digital). Connect to DNA through a data transformer.

VDD (Pins 12, 19, 24): VDD IO Power Supply. Connect

to a 3.3V power supply relative to DGND. Each VDD pin

must be locally bypassed with at least a 0.1µF capacitor.

A 10µF bulk capacitor must be connected across VDD for

increased surge immunity.

RESET (Pin 14): Reset Input, Active Low. When RESET is

low, the LTC9101-2/LTC9102 is held inactive with all ports

off and all internal registers reset. When RESET is pulled

high, the LTC9101-2/LTC9102 begins normal operation.

RESET can be connected to an external capacitor or RC

network to provide a power turn-on delay. Internal filtering

of RESET prevents glitches less than 1µs wide from reset-

ting the LTC9101-2/LTC9102. Internally pulled up to VDD.

INT (Pin 15): Interrupt Output, Open Drain. INT will pull low

when any one of several events occur in the LTC9101-2. It

will return to a high impedance state when bits 6 or 7 are set

in the Reset register. The INT signal can be used to generate

an interrupt to the host processor, eliminating the need for

continuous software polling. Individual INT events can be

disabled using the Int Mask register. See LTC9101-2NDASI

Software Programming documentation for more information.

INT is only updated between I2C transactions.

SDAOUT (Pin 16): Serial Data Output, Open Drain Data

Output for the I2C Serial Interface Bus. The LTC9101-2 uses

two pins to implement the bidirectional SDA function to sim-

plify opto isolation of the I2C bus. To implement a standard

bidirectional SDA pin, tie SDAOUT and SDAIN together. See

Applications Information for more information.

SDAIN (Pin 17): Serial Data Input. High impedance data

input for the I2C serial interface bus. The LTC9101-2 uses

two pins to implement the bidirectional SDA function to

simplify opto isolation of the I2C bus. To implement a stan-

dard bidirectional SDA pin, tie SDAOUT and SDAIN together.

See Applications Information for more information.

SCL (Pin 18): Serial Clock Input. High impedance clock

input for the I2C serial interface bus. The SCL pin should

be connected directly to the I2C SCL bus line. SCL must

be tied high if the I2C serial interface bus is not used.

OSS (Pin 20): Maskable Shutdown Input, Active High.

Supports both 1-bit shutdown priority and 3-bit shutdown

priority. See Over Supply Shutdown (OSS) section for

details. Internally pulled down to DGND.

AD[4:1] (Pins 21, 6, 5, 3 Respectively): I2C Address Bits

4 to 1. Tie the address pins high or low to set the base I2C

serial address. The base address will be (01A4A3A2A10b).

Internally pulled up to VDD. See Bus Addressing for details.

DGND (Pins 22, 25): Digital Ground. DGND should be

connected to the return from the VDD supply.

LTC9102

CAP3 (Pin 1): Analog Internal 3.3V Power Supply Bypass

Capacitor. Connect a 1μF ceramic cap to VEE. A 3.3V power

supply may be connected to this pin to improve power

supply efficiency. The EXT3 pin must be pulled to CAP3

to shut off the internal 3.3V regulator if power is supplied

externally. Do not source or sink current from this pin.

Do not connect to CAP3 except as explicitly instructed

in ADI documentation (e.g., strapping LTC9102 pins and

terminating the serial interface).

EXT3 (Pin 2): External 3.3V Enable. Connect the EXT3

pin to CAP3 to shut off the internal 3.3V regulator when

power is supplied externally. Float or connect to VEE for

internal regulator operation.

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