MEC1632 datasheet(106/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 106

 2012-2018 Microchip Technology Inc.

When firmware de-asserts the internal block enable bit the block is disabled and in a minimum power consumption

state. Depending on the implementation, the host may need to ensure that the block is not in use before the internal

enable bit is de-asserted because it may also function as a reset. Transitions to a minimum block power consumption

state while the internal enable bit remains asserted may be requested by the Power Management Interface using an

external sleep enable input (see also Section 7.4.8.3, "Behavior," on page 107). In both cases (i.e., when the block is

disabled or sleeping), the core clock required status indicator output (BLK_CLK_REQ in Figure 7-10) is de-asserted.

When firmware asserts the internal block enable and the external sleep enable input is not asserted, or the external

sleep enable input is asserted but the internal idle indicator is not asserted, the block is operational and in a maximum

power consumption state. In both of these cases, the core clock required status indicator output is asserted.

Note 7-14

the “Block Clock Required Status Output” (BLK_CLK_REQ in Figure 7-10) only reflects the core clock

requirement; i.e. independent of the host interface clock enable (EC_HOST_BUS_CLK_EN in

Figure 7-10). The MEC1632 Generic Block Clocking Model assumes that the block may not remain

operational without the host interface clock enable which will not be stopped unless the 20 MHz

Oscillator is disabled (see Section 7.4.10, "Power Management Interface," on page 111). The “Clock

Required Status” for each block can be seen in the Clock Required Status Registers.

Note 7-15

the internal enable bit (not shown in Figure 7-10) is accessible through the EC Host Interface shown

in Figure 7-10 and provides a reset to each block. Typically, as soon as the internal enable bit is

de-asserted, the block may be immediately reset and held in the lowest power consumption state.

Note 7-16

The external sleep enables are configured using the Block Sleep Enables as described in "Block

Sleep Enables," on page 117.

TABLE 7-11:

Generic Block Clocking Model COMPONENTS

Internal

Enable Bit

(

Note 7-15)

External

SLEEP_EN

Input

(

Note 7-16)

Block Idle

Status

Core Clock

Required

Status Output

(

Note 7-14)

State

Power

Description

DISABLED

MINIMUM

Block is disabled by firm-

ware and the core clock is

not needed and gated ‘off’

internally. Note: it may

be up to the host to

ensure that the block is

not in use before the inter-

nal enable bit is de-

asserted because the

internal enable may also

function as a reset when

not asserted.

NOT IDLE

FULL POWER MAXIMUM The full power state iden-

tifies the block normal

operation mode where the

block is neither disabled

by firmware nor com-

manded to sleep by the

Power Management Inter-

face.

IDLE

NOT IDLE

PREPARING

TO SLEEP

A sleep command has

been asserted but the

core clock is still required

because the block is not

idle.

IDLE

SLEEPING

MINIMUM

A sleep command has

been asserted, the block

is idle and the core clocks

are stopped (Note 7-17).

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