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RT600 Datasheet(PDF) 128 Page - NXP Semiconductors

Part # RT600
Description  Dual-core microcontroller with 32-bit Cortex®-M33 and Xtensa HiFi4 Audio DSP CPUs; Up to 4.5 MB SRAM; FlexSPI with cache and dynamic decryption; High-speed USB device/host
PDF  171 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

RT600 Datasheet(HTML) 128 Page - NXP Semiconductors

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RT600
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2023. All rights reserved.
Product data sheet
Rev. 2.1 — 7 July 2023
128 of 173
NXP Semiconductors
RT600
Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4
Audio DSP CPUs
tsu(D)
data input set-up time
on pins SD_DATn as inputs
4.8
-
-
ns
on pins SD_CMD as inputs
4.8
-
-
ns
th(D)
data input hold time
on pins SD_DATn as inputs
0
-
-
ns
on pins SD_CMD as inputs
0
-
-
ns
tv(Q)
data output valid time
on pins SD_DATn as outputs
0
-
5.0
ns
on pins SD_CMD as outputs
0
-
5.0
ns
Table 48. Dynamic characteristics for following modes (DDR-50, DDR-100, HS DDR)
Tamb = -0 C to +85 C, VDDIO_x = 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF. DLL_CTRL = 0x200, Full Drive Mode
on all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the rising
or falling edge. Based on simulation, not tested in production. HS-400 supported on SD port 0 only.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 49. Dynamic characteristics for following modes (DDR-200 (HS-400))
Tamb = -0 C to +85 C, VDDIO_x = 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF. DLL_CTRL = 0x200, Full Drive Mode
on all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the rising
or falling edge. Based on simulation, not tested in production. HS-400 supported on SD port 0 only.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk
clock frequency
on pin SD_CLK; data transfer mode,
DDR-200 (HS-400) (400 MB/s)
-
-
200
MHz
tsu(D)
data input set-up time
on pins SD_DATn as inputs
0.5
-
-
ns
on pins SD_CMD as inputs
0.5
-
-
ns
th(D)
data input hold time
on pins SD_DATn as inputs
0
-
-
ns
on pins SD_CMD as inputs
0
-
-
ns
tv(Q)
data output valid time
on pins SD_DATn as outputs
0
-
1.0
ns
on pins SD_CMD as outputs
0
-
1.0
ns



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