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TMS320DM355 Datasheet(PDF) 107 Page - Texas Instruments

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Part # TMS320DM355
Description  Digital Media System-on-Chip (DMSoC)
PDF  153 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM355 Datasheet(HTML) 107 Page - Texas Instruments

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TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463 – SEPTEMBER 2007
Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15) (continued)
DM355
UNI
NO.
PARAMETER
T
MIN
Nom
MAX
Output setup time, EM_BA[1:0] valid to
6
tsu(EMBAV-EMOEL)
(RS)*E
ns
EM_OE low
Output hold time, EM_OE high to
7
th(EMOEH-EMBAIV)
(RH)*E
ns
EM_BA[1:0] invalid
Output setup time, EM_A[13:0] valid to
8
tsu(EMBAV-EMOEL)
(RS)*E
ns
EM_OE low
Output hold time, EM_OE high to
9
th(EMOEH-EMAIV)
(RH)*E
ns
EM_A[13:0] invalid
EM_OE active low width (EW = 0)
(RST)*E
ns
10
tw(EMOEL)
EM_OE active low width (EW = 1)
(RST+(EWC*16))*E
ns
td(EMWAITH-
Delay time from EM_WAIT deasserted to
11
4E
ns
EMOEH)
EM_OE high
READS (OneNAND Synchronous Burst Read)
MH
32
fc(EM_CLK)
Frequency, EM_CLK
1
66
z
33
tc(EM_CLK)
Cycle time, EM_CLK
15
1000
ns
tsu(EM_AVDV-
Output setup time, EM_AVD valid before
34
5
ns
EM_CLKH)
EM_CLK high
th(EM_CLKH-
Output hold time, EM_CLK high to EM_AVD
35
6
ns
EM_AVDIV)
invalid
tsu(EM_AV-
Output setup time, EM_A[13:0]/EM_BA[1]
36
5
ns
EM_CLKH)
valid before EM_CLK high
th(EM_CLKH-
Output hold time, EM_CLK high to
37
6
ns
EM_AIV)
EM_A[13:0]/EM_BA[1] invalid
38
tw(EM_CLKH)
Pulse duration, EM_CLK high
tc(EM_CLK)/3
ns
39
tw(EM_CLKL)
Pulse duration, EM_CLK low
tc(EM_CLK)/3
ns
WRITES
EMIF write cycle time (EW = 0)
(WS+WST+WH)*E
ns
15
tc(EMWCYCLE)
(WS+WST+WH+(EW
EMIF write cycle time (EW = 1)
ns
C*16))*E
Output setup time, EM_CE[1:0] low to
(WS)*E
ns
EM_WE low (SS = 0)
16
tsu(EMCEL-EMWEL)
Output setup time, EM_CE[1:0] low to
0
ns
EM_WE low (SS = 1)
Output hold time, EM_WE high to
(WH)*E
ns
EM_CE[1:0] high (SS = 0)
17
th(EMWEH-EMCEH)
Output hold time, EM_WE high to
0
ns
EM_CE[1:0] high (SS = 1)
Output setup time, EM_BA[1:0] valid to
20
tsu(EMBAV-EMWEL)
(WS)*E
ns
EM_WE low
Output hold time, EM_WE high to
21
th(EMWEH-EMBAIV)
(WH)*E
ns
EM_BA[1:0] invalid
Output setup time, EM_A[13:0] valid to
22
tsu(EMAV-EMWEL)
(WS)*E
ns
EM_WE low
Output hold time, EM_WE high to
23
th(EMWEH-EMAIV)
(WH)*E
ns
EM_A[13:0] invalid
EM_WE active low width (EW = 0)
(WST)*E
ns
24
tw(EMWEL)
EM_WE active low width (EW = 1)
(WST+(EWC*16))*E
ns
td(EMWAITH-
Delay time from EM_WAIT deasserted to
25
4E
ns
EMWEH)
EM_WE high
Output setup time, EM_D[15:0] valid to
26
tsu(EMDV-EMWEL)
(WS)*E
ns
EM_WE low
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Peripheral Information and Electrical Specifications
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