TMS320DM355 datasheet(141/153 Pages) TI

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Bit0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit0

Bit(n-1)

(n-2)

(n-3)

(n-4)

M39

M36

M38

M37

M35

M34

CLKX

FSX

M40

M42

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

Table 5-39. ASP as SPI Timing Requirements

CLKSTP = 11b, CLKXP = 0

MASTER

NO.

UNIT

MIN

MAX

M39

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

M40

th(CKXH-DRV)

Hold time, DR valid after CLKX high

Table 5-40. ASP as SPI Switching Characteristics(1)(2)

CLKSTP = 11b, CLKXP = 0 (see Figure 5-43)

MASTER

NO.

PARAMETER

UNIT

MIN

MAX

38.5 or

M42

tc(CKX)

Cycle time, CLKX

2P(1)(3)

M34

td(CKXL-FXH)

Delay time, CLKX low to FSX high(4)

C – 2

C + 3

M35

td(FXL-CKXH)

Delay time, FSX low to CLKX high(5)

T – 2

T + 2

M36

td(CKXL-DXV)

Delay time, CLKX low to DX valid

–2

Disable time, DX high impedance following last data bit from

M37

tdis(CKXL-DXHZ)

–3

CLKX low

M38

td(FXL-DXV)

Delay time, FSX low to DX valid

D – 2

D + 10

(1)

P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .

(2)

T = CLKX period = (1 + CLKGDV)

× P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2)

× P when CLKGDV is even

D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1)

× P when CLKGDV is even

(3)

Use which ever value is greater.

(4)

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP

(5)

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master

clock (CLKX).

Figure 5-43. ASP as SPI: CLKSTP = 11b, CLKXP = 0

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