TMS320DM355 datasheet(138/153 Pages) TI

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5.14.1

ASP Electrical Data/Timing

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

5.14.1.1

Audio Serial Port (ASP) Timing

Table 5-35. Timing Requirements for ASP(1) (see Figure 5-41)

DM355

NO.

UNIT

MIN

MAX

tc(CLK)

Cycle time, CLK

CLK ext

38.5 or 2P(2)(3)

OTG(CLKS)

Pulse duration, CLKR/X high or CLKR/X low

CLKS ext

19.25 or P(2)(3)(4)

CLKR int

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR ext

CLKR int

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR ext

CLKR int

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR ext

CLKR int

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR ext

CLKX int

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX ext

CLKX int

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX ext

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .

(3)

Use which ever value is greater.

(4)

The ASP does not have a duty cycle specification, just ensure that the minimum pulse duration specification is met.

Peripheral Information and Electrical Specifications

138

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