TMS320DM355 datasheet(139/153 Pages) TI

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Bit(n-1)

(n-2)

(n-3)

Bit0

Bit(n-1)

(n-2)

(n-3)

13(A)

A. ParameterNo.13appliestothefirstdatabitonly whenXDATDLY ≠ 0.

CLKR

FSR(int)

FSR(ext)

CLKX

FSX(int)

FSX(ext)

FSX

(XDATDLY=00b)

CLKS

TMS320DM355

Digital Media System-on-Chip (DMSoC)

SPRS463 – SEPTEMBER 2007

Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP(1)(2)

(see Figure 5-41)

DM355

NO.

PARAMETER

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

38.5 or 2P(3)(4)

td(CLKS-CLKRX)

Delay time, CLKS high to internal CLKR/X

CLKR/X int

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

C - 1

C + 1

CLKR int

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR ext

CLKX int

-4

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

CLKX int

tdis(CKXH-

Disable time, DX high impedance following last data

DXHZ)

bit from CLKX high

CLKX ext

CLKX int

-5

td(CKXH-DXV)

Delay time, CLKX high to DX valid

CLKX ext

Delay time, FSX high to DX valid

FSX int

14(5)

td(FXH-DXV)

ONLY applies when in data

FSX ext

25(5)

delay 0 (XDATDLY = 00b) mode

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

Minimum delay times also represent minimum output hold times.

(3)

P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .

(4)

Use which ever value is greater.

(5)

Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

Figure 5-41. ASP Timing

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