IMX93CEC datasheet(2/126 Pages) NXP

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i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

i.MX 93 introduction

•Smart lock

•

Smart thermostat

•

Smart docking station

Table 1. Features (Sheet 1 of 3)

Subsystem

Features

Cortex®-A55 MPCore platform

Two Cortex®-A55 processors operating up to 1.7 GHz

• 32 KB L1 Instruction Cache

• 32 KB L1 Data Cache

• 64 KB per-core L2 cache

• Media Processing Engine (MPE) with Arm® NeonTM technology supporting the

Advanced Single Instruction Multiple Data architecture

• Floating Point Unit (FPU) with support of the Arm® VFPv4-D16 architecture

Support of 64-bit Arm® v8.2-A architecture

256 KB cluster L3 cache

Parity/ECC protection on L1 cache, L2 cache, and TLB RAMs

Cortex®-M33 core platform

• Stand by monitoring with Cortex®-A55 and other high-power modules power

gated

Cortex®-M33 CPU operating up to 250 MHz

• Support FPU

• Support MPU

• Support NVIC

• Support FPB

• Support DWT and ITM

• Two-way set-associative 16 KB System Cache with parity support

• Two-way set-associative 16 KB Code Cache with parity support

• 256 KB tightly coupled memory (TCM)

Neural Processing Unit (NPU)

Neural Network performance (256 MACs operating up to 1.0 GHz and 2 OPS/MAC)

• NPU targets 8-bit and 16-bit integer RNN

• Handles 8-bit weights

Image Sensor Interface (ISI)

• Standard pixel formats commonly used in many camera input protocols

• Programmable resolutions up to 2K

• Image processing for:

•Supports one source of up to 2K horizontal resolution

•Supports pixel rate up to 200 Mpixel/s

• Image down scaling via decimation and bi-phase filtering

• Color space conversion

• Interlaced to progressive conversions

On-chip memory

Boot ROM (256 KB) for Cortex®-A55

Boot ROM (256 KB) for Cortex®-M33

On-chip RAM (640 KB)

General Business Information

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