IMX93CEC datasheet(66/126 Pages) NXP

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i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

Electrical characteristics

4.12.3.4 RGMII signal switching specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver

devices.

Table 68. MII serial management channel timing1,2,3

1 The timings assume the following configuration: CTL[5:0] = 001111 and SL[1:0] = 11.

2 Input timing assumes an input signal slew rate of 3 ns (20%/80%).

3 Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm.

Unterminated, 5-inch microstrip trace on standard FR4 (1.5 pF/inch), (25 pF total with margin). For best signal integrity, the

series resistance in the transmission line should be equal to the selected RDSON of the I/O pad output driver.

Characteristic

Min.

Max.

Unit

M10

ENET_MDC falling edge to ENET_MDIO output invalid (min.

propagation delay)

-1.5

—

M11

ENET_MDC falling edge to ENET_MDIO output valid (max.

propagation delay)

—13

M12

ENET_MDIO (input) to ENET_MDC rising edge setup

—

M13

ENET_MDIO (input) to ENET_MDC rising edge hold

—

M14

ENET_MDC pulse width high

40%

60%

ENET_MDC period

M15

ENET_MDC pulse width low

40%

60%

ENET_MDC period

Table 69. RGMII signal switching specifications1,2,3,4

1 The timings assume the following configuration: CTL[5:0] = 001111 and SL[1:0] = 11.

2 Measured as defined in EIA/JESD 8-6 1995 with a timing threshold voltage of VDDQ/2.

3 Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 8 pF load at the end of a 50 ohm,

unterminated, 2-inch microstrip trace on standard FR4 (1.5 pF/inch). For best signal integrity, the series resistance in the

transmission line should be matched closely to the selected RDSON of the I/O pad output driver.

4 RGMII timing specifications are only valid for 1.8 V nominal I/O pad supply voltage.

Symbol

Description

Min.

Max.

Unit

Tcyc

Clock cycle duration

7.2

8.8

TskewT

Data to clock output skew at transmitter

-500

500

TskewR

Data to clock input skew at receiver

2.6

Duty_G

Duty cycle for Gigabit

Duty_T

Duty cycle for 10/100T

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