IMX93CEC datasheet(4/126 Pages) NXP

4 / 126 page

i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

i.MX 93 introduction

1.1

Ordering information

Table 2 provides examples of orderable part numbers covered by this Data Sheet.

Power management

Temperature sensor with programmable trip points

Flexible power domain partitioning with internal power switches to support efficient

power management

Connectivity

Two USB 2.0 controllers and PHYs interfaces

Two Controller Area Network (FlexCAN) modules, each optionally supporting flexible

data-rate (FD)

Two Improved Inter Integrated Circuit (I3C) modules

Two 32-pin FlexIO modules

Three Ultra Secure Digital Host Controller (uSDHC) interfaces

Two Ethernet controllers (capable of simultaneous operation)

• One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),

Ethernet AVB, and IEEE 1588

• One Gigabit Ethernet controller with support for TSN in addition to EEE, Ethernet

AVB, and IEEE 1588

Eight Low Power SPI (LPSPI) modules

Eight Low Power I2C modules

Eight Low Power Universal Asynchronous Receiver/Transmitter (LPUART) modules

Security

Trusted Resource Domain Controller (TRDC)

• Supports 16 domains

Arm® TrustZone® (TZ) architecture, including both Trustzone-A and Trustzone-M

On-chip RAM (OCRAM) secure region protection using OCRAM controller

EdgeLock® secure enclave

Battery Backed Security Module (BBSM)

• Secure real-time clock (RTC)

System debug

Arm® CoreSightTM debug and trace technology

Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering

Unified trace capability for dual core Cortex®-A55 and Cortex®-M33 CPUs

Cross Triggering Interface (CTI)

Support for 4-pin (JTAG) debug interface and SWD

Table 1. Features (continued) (Sheet 3 of 3)

Subsystem

Features

General Business Information

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