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IMX93CEC Datasheet(PDF) 96 Page - NXP Semiconductors |
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IMX93CEC Datasheet(HTML) 96 Page - NXP Semiconductors |
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96 / 126 page  i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023 96 NXP Semiconductors Package information and contact assignments DRAM_CS1_A G2 VDDQ_DDR DDR — — — DRAM_DMI0_A L2 VDDQ_DDR DDR — — — DRAM_DMI1_A T2 VDDQ_DDR DDR — — — DRAM_DQ00_A N1 VDDQ_DDR DDR — — — DRAM_DQ01_A N2 VDDQ_DDR DDR — — — DRAM_DQ02_A M1 VDDQ_DDR DDR — — — DRAM_DQ03_A M2 VDDQ_DDR DDR — — — DRAM_DQ04_A K1 VDDQ_DDR DDR — — — DRAM_DQ05_A K2 VDDQ_DDR DDR — — — DRAM_DQ06_A J1 VDDQ_DDR DDR — — — DRAM_DQ07_A J2 VDDQ_DDR DDR — — — DRAM_DQ08_A V1 VDDQ_DDR DDR — — — DRAM_DQ09_A V2 VDDQ_DDR DDR — — — DRAM_DQ10_A U2 VDDQ_DDR DDR — — — DRAM_DQ11_A U1 VDDQ_DDR DDR — — — DRAM_DQ12_A R1 VDDQ_DDR DDR — — — DRAM_DQ13_A R2 VDDQ_DDR DDR — — — DRAM_DQ14_A P2 VDDQ_DDR DDR — — — DRAM_DQ15_A P1 VDDQ_DDR DDR — — — DRAM_DQS0_C_A L4 VDDQ_DDR — — — — DRAM_DQS0_T_A N4 VDDQ_DDR DDRCLK — — — DRAM_DQS1_C_A R5 VDDQ_DDR — — — — DRAM_DQS1_T_A R4 VDDQ_DDR DDRCLK — — — DRAM_MTEST1 D4 VDDQ_DDR DDR — — — DRAM_RESET_N D2 VDDQ_DDR DDR — — — DRAM_ZQ E4 VDDQ_DDR DDR — — — ENET1_MDC AA11 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[0] Input with PD ENET1_MDIO AA10 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[1] Input with PD ENET1_RD0 AA8 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[10] Input with PD ENET1_RD1 Y9 NVCC_WAKEUP GPIO Alt5 GPIO4.IO[11] Input with PD Table 106. 11 x 11 mm functional contact assignment (continued) Ball name 11 x 11 ball Power group Ball Types Default setting Default modes Default function Status while reset is asserted General Business Information |
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