IMX93CEC datasheet(3/126 Pages) NXP

3 / 126 page

i.MX 93 introduction

i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

External memory interface

16-bit DRAM interface:

• LPDDR4X/LPDDR4 with inline ECC

Three Ultra Secure Digital Host Controller (uSDHC) interfaces:

• One eMMC 5.1 (8-bit) compliance with HS400 DDR signaling to support up to 400

MB/sec

• One SDXC (4-bit, no eMMC5.1, with extended capacity)

• One SDIO (4-bit, SD/SDIO 3.01 compliance with 200 MHz SDR signaling and up

to 100 MB/sec)

FlexSPI Flash with support for XIP (for Cortex®-A55 in low-power mode) and support

for either one Octal SPI or Quad SPI FLASH device. It also supports both Serial NOR

and Serial NAND flash using the FlexSPI.

Pixel Pipeline (PXP)

• BitBlit

• Flexible image composition options—alpha, chroma key

• Porter-Duff operation

• Image rotation (90o, 180o, 270o)

• Image resize

• Color space conversion

• Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)

• Standard 2D-DMA operation

LCDIF Display Controller

The LCDIF can drive any of three displays:

• MIPI DSI: up to 1920x1200p60

• LVDS Tx: up to 1366x768p60 or 1280x800p60

• Parallel display: up to 1366x768p60 or 1280x800p60

MIPI CSI-2 Interface

One 2-lane MIPI CSI-2 camera input:

• Complaint with MIPI CSI-2 specification v1.3 and MIPI D-PHY specification v1.2

• Support up to 2 Rx data lanes (plus 1 Rx clock lane)

• Support 80 Mbps – 1.5 Gbps per lane data rate in high speed operation

• Support 10 Mbps data rate in low power operation

MIPI DSI Interface

One 4-lane MIPI DSI display with data supplied by the LCDIF

• Compliant with MIPI DSI specification v1.2 and MIPI D-PHY specification v1.2

• Capable of resolutions achievable with a 200 MHz pixel clock and active pixel rate

of 140 Mpixel/s with 24-bit RGB.

• Support 80 Mbps—1.5 Gbps data rate per lane in high speed operation

• Support 10 Mbps data rate in low power operation

Audio

• Three SAI interfaces:

•SAI1 supports 2-lane and SAI3 supports 1 lane

•SAI2 support 4 lanes

•SAI2 and SAI3 support glue-less switching between PCM and stereo DSD

operation

• One SPDIF supports raw capture mode that can save all the incoming bits into

audio buffer

• 24-bit PDM supports up to 8-microphones (4 lanes)

GPIO and input/output multiplexing

General-purpose input/output (GPIO) modules with interrupt capability

Input/output multiplexing controller (IOMUXC) to provide centralized pad control

Table 1. Features (continued) (Sheet 2 of 3)

Subsystem

Features

General Business Information

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