IMX93CEC datasheet(13/126 Pages) NXP

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i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

3.1

Special signal considerations

Table 4 lists special signal considerations for the i.MX 93 processors. The signal names are listed in

alphabetical order.

The package contact assignments can be found in Section 6, Package information and contact

assignments.” Signal descriptions are provided in the i.MX 93 Reference Manual (IMX93RM).

3.2

Unused input and output guidance

If a function of the i.MX 93 is not used, the I/Os and power rails of that function can be terminated to

reduce overall board power. Table 5 is recommended connectivities for LVDS and other digital I/Os. Table

6 is recommended connectivities for MIPI. Table 7 is recommended connectivities for USB.

Table 4. Special signal considerations

Signal Name

Remarks

CLKIN1/CLKIN2

CLKIN1 and CLKIN2 are input pins without internal pull-up and pull-down. An external 10K

pull-down resistor is recommended if they are not used.

These signals are No Connect (NC) and should be unconnected in the application.

ONOFF

A brief connection to GND in the OFF mode causes the internal power management state machine

to change the state to ON. In the ON mode, a brief connection to GND generates an interrupt

(intended to be a software-controllable power-down). Approximately five seconds (or more) to GND

causes a forced OFF.

POR_B

POR_B has no internal pull-up/down resistor, and requires external pull-up resistor to

NVCC_BBSM_1P8.

It is recommended that POR_B is properly handled during power up/down. Please see the EVK

design for details.

RTC_XTALI/RTC_XTALO To hit the exact oscillation frequency, the board capacitors must be reduced to account for the

board and chip parasitics. The integrated oscillation amplifier is self-biasing, but relatively weak.

Care must be taken to limit the parasitic leakage from RTC_XTALI and RTC_XTALO to either the

power or the ground (> 100 M

). This de-biases the amplifier and reduces the start-up margin.

If you want to feed an external low-frequency clock into RTC_XTALI, the RTC_XTALO pin must

remain unconnected or driven by a complementary signal. The logic level of this forcing clock must

not exceed the NVCC_BBSM_1P8 level and the frequency shall be < 50 kHz under the typical

conditions.

XTALI_24M/XTALO_24M The system requires 24 MHz on XTALI/XTALO. The crystal cannot be eliminated by the external

24 MHz oscillator.

The logic level of this forcing clock must not exceed the VDD_ANA0_1P8 level.

If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter

requirements. See Section 4.1.6, Clock sources and relevant interface specifications chapters for

details.

Table 5. Unused function strapping recommendations

Function

Ball name

Recommendations

if unused

ADC

ADC_IN0, ADC_IN1, ADC_IN2, ADC_IN3

Tie to ground

TAMPER TAMPER0, TAMPER1

Tie to ground

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