IMX93CEC datasheet(56/126 Pages) NXP

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i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

Electrical characteristics

Table 58. HS200 interface timing specification (Nominal and Overdrive mode)1,2

1 Input timing assumes an input signal slew rate of 1 ns (20%/80%).

2 Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 8 pF load at the end of a 50 ohm,

unterminated, 2-inch microstrip trace on standard FR4 (1.5 pF/inch). For best signal integrity, the series resistance of the

transmission line should be matched closely to the RDSON of the I/O pad output driver.

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

5.0

—

SD2

Clock Low Time

tCL

2.2

—

SD3

Clock High Time

tCH

2.2

—

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

-1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)3

3 HS200 is for 8 bits while SDR104 is for 4 bits.

SD8

uSDHC Input Data Window

tODW

0.475 x

tCLK

—ns

Table 59. HS200 interface timing specification (Low drive mode)1,2

1 Input timing assumes an input signal slew rate of 1 ns (20%/80%).

2 Output timing valid for maximum external load CL = 15 pF, which is assumed to be a 8 pF load at the end of a 50 ohm,

unterminated, 2-inch microstrip trace on standard FR4 (1.5 pF/inch). For best signal integrity, the series resistance of the

transmission line should be matched closely to the RDSON of the I/O pad output driver.

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency Period

tCLK

7.5

—

SD2

Clock Low Time

tCL

3.3

—

SD3

Clock High Time

tCH

3.3

—

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

SD5

uSDHC Output Delay

tOD

-1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)3

3 HS200 is for 8 bits while SDR104 is for 4 bits.

SD8

uSDHC Input Data Window

tODW

0.475 x

tCLK

—ns

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