IMX93CEC datasheet(76/126 Pages) NXP

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i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

Electrical characteristics

4.12.8 Timer/Pulse width modulator (TPM) timing parameters

This section describes the output timing parameters of the TPM.

The CTL[5:0] = 001111 and SL[1:0] = 11 are required drive settings to meet the timing.

Figure 43 depicts the timing of the PWM, and Table 77 lists the TPM timing parameters.

Figure 43. TPM timing

4.12.9 FlexSPI timing parameters

The FlexSPI interface can work in SDR or DDR modes. Only FlexSPIn_MCR0[RXCLKSRC] = 0 and

FlexSPIn_MCR0[RXCLKSRC] = 1 configurations are supported when I/O is supplied by 3.3 V.

Input timing assumes an input signal slew rate of 1 ns (20%/80%) and Output timing valid for maximum

external load CL = 15 pF, which is assumed to be a 8 pF load at the end of a 50 ohm, un-terminated, 2-inch

microstrip trace on standard FR4 (1.5 pF/inch). For best signal integrity, the series resistance of the

transmission line should be matched closely to the selected RDSON of the I/O pad output driver.

TX routing delay wcs

5/5

RX routing delay wcs

5/5

Transceiver loop delay wcs

250/250

190/190

Total loop delay

395/345

285/247.5

Table 77. TPM output timing parameters

Parameter

Min

Max

Unit

PWM Module Clock Frequency

83.3

MHz

PWM output pulse width high

—

PWM output pulse width low

—

Table 76. CAN-FD electrical specifications (continued)

Parameters

BCAN (Classical and

FD)

FlexCAN (Classical

and FD)

BCANXL (Classical,

FD, and XL)

Unit

TPM_CHn

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