IMX93CEC datasheet(46/126 Pages) NXP

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i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

Electrical characteristics

Figure 17. SPDIF_SR_CLK timing diagram

Figure 18. SPDIF_ST_CLK timing diagram

4.10.3 PDM Microphone interface timing parameters

NOTE

These timing requirements apply only if the clock divider is enabled

(PDM_CTRL2[CLKDIV] = 0), otherwise there are no special timing

requirements.

The PDM microphones must meet the setup and hold timing requirements shown in the following table. The “k”

factor value in Table 49 depends on the selected quality mode as shown in Table 50.

SPDIF_SR_CLK low period

srckpl

16.0

—

Modulating Tx clock (SPDIF_ST_CLK) period

stclkp

40.0

—

SPDIF_ST_CLK high period

stclkph

16.0

—

SPDIF_ST_CLK low period

stclkpl

16.0

—

Table 49. PDM timing parameters

Parameter

Value

trs, tfs

1 @moduleNickname = PDM. Depending on K value, user must make sure floor (K x CLKDIV) > 1 to avoid timing problems.

trh, tfh

>= 0

Table 48. SPDIF timing parameters (continued)

Parameter

Symbol

Timing Parameter Range

Unit

Min

Max

SPDIF_SR_CLK

(Output)

srckp

srckph

srckpl

SPDIF_ST_CLK

(Input)

stclkp

stclkph

stclkpl

@(moduleNickname)_CLK_ROOTrate

floor (kxCLKDIV) - 1

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