IMX93CEC datasheet(10/126 Pages) NXP

10 / 126 page

i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

Modules list

LCDIF

LCD Interface

The LCD Interface (LCDIF) is, a general purpose display controller,

used to drive a wide range of display devices varying in size and

capability.

LDB

LVDS Display Bridge

LVDS Display Bridge provides the following functionalities:

• Connectivity to relevant devices - Displays with LVDS receivers.

• Arranging the data as required by the external display receiver

and by LVDS display standards.

• Synchronization and control capabilities.

LPI2C1

LPI2C2

LPI2C3

LPI2C4

LPI2C5

LPI2C6

LPI2C7

LPI2C8

Low Power Inter-integrated

Circuit

The LPI2C is a low power Inter-Integrated Circuit (I2C) module that

supports an efficient interface to an I2C bus as a controller and/or as

a target.

The I2C provides a method of communication between a number of

external devices. More detailed information, see Section 4.12.5,

LPI2C timing parameters.

LPSPI1

LPSPI2

LPSPI3

LPSPI4

LPSPI5

LPSPI6

LPSPI7

LPSPI8

Low Power Serial Peripheral

Interface

The LPSPI is a low power Serial Peripheral Interface (SPI) module

that support an efficient interface to an SPI bus as a master and/or a

slave.

• It can continue operating while the chip is in stop modes, if an

appropriate clock is available

• Designed for low CPU overhead, with DMA off loading of FIFO

LPUART1

LPUART2

LPUART3

LPUART4

LPUART5

LPUART6

LPUART7

LPUART8

Low Power UART Interface

Each of the LPUART modules support the following serial data

transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even,

odd or none)

• Programmable baud rates up to 5 Mbps.

MIPI CSI-2

MIPI CSI-2 Interface

Key features of MIPI CSI-2 controller are listed as following:

• Complaint with MIPI CSI-2 specification v1.3 and MIPI D-PHY

specification v1.2

• Support up to 2 Rx data lanes (plus 1 Rx clock lane)

• MIPI CSI-2 supports:

– Pixel clock up to 200 MHz (at both nominal and overdrive

voltage)

– Up to approximately 150 Mpixel/s supported

– 80 Mbps to 1.5 Gbps per lane data rate in high speed operation

• Support 10 Mbps data rate in low power operation

Table 3. i.MX 93 modules list (continued)

Block mnemonic

Block name

Brief description

General Business Information

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