IMX93CEC datasheet(43/126 Pages) NXP

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Electrical characteristics

i.MX 93 Application Processors Data Sheet for Commercial Products, Rev. 3, 12/2023

NXP Semiconductors

The CTL[5:0] = 001111 and SL[1:0] = 11 are required drive settings to meet the timing.

For the 50 MHz BCLK operation, the BCLK and SYNC must always be in the same direction as the data

(source synchronous):

•

SAI transmitter must be in asynchronous mode with BCLK and SYNC configuration as outputs

•

SAI receiver must be:

— In asynchronous mode with BCLK and SYNC configuration as inputs

— In synchronous mode with SAI_RCR2[BCI] = 1

Table 45. Master mode SAI timing (50 MHz)1,2,3

1 To achieve 50 MHz for BCLK operation, clock must be set in feedback mode.

2 Input timing assumes an input signal slew rate of 3 ns (20%/80%).

3 Output timing valid for maximum external load CL = 25 pF, which is assumed to be a 10 pF load at the end of a 50 ohm.

Unterminated, 5-inch microstrip trace on standard FR4 (1.5 pF/inch), (25 pF total with margin). For best signal integrity, the

series resistance in the transmission line should be equal to the selected RDSON of the I/O pad output driver.

Num

Characteristic

Min

Max

Unit

SAI_MCLK cycle time

—

SAI_MCLK pulse width high/low

40%

60%

MCLK period

SAI_BCLK cycle time

—

SAI_BCLK pulse width high/low

40%

60%

BCLK period

SAI_BCLK to SAI_FS output valid

—

SAI_BCLK to SAI_FS output invalid

-2

—

SAI_BCLK to SAI_TXD valid

—

SAI_BCLK to SAI_TXD invalid

-2

—

SAI_RXD/SAI_FS input setup before SAI_BCLK

—

S10

SAI_RXD/SAI_FS input hold after SAI_BCLK

—

Table 46. Master mode SAI timing (25 MHz)1,2

Num

Characteristic

Min

Max

Unit

SAI_MCLK cycle time

—

SAI_MCLK pulse width high/low

40%

60%

MCLK period

SAI_BCLK cycle time

—

SAI_BCLK pulse width high/low

40%

60%

BCLK period

SAI_BCLK to SAI_FS output valid

—

SAI_BCLK to SAI_FS output invalid

-2

—

SAI_BCLK to SAI_TXD valid

—

SAI_BCLK to SAI_TXD invalid

-2

—

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