PM7347 datasheet(289/341 Pages) PMC

289 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

289

Document ID: PMC-1990267, Issue 3

The boundary scan architecture consists of:

• A TAP controller.

• An instruction register with instruction decode.

• A bypass register

• A device identification register

• A boundary scan register.

The TAP controller interprets the TMS input and generates control signals to load the instruction

and data registers. The instruction register with instruction decode block is used to select the test

to be executed and/or the register to be accessed. The bypass register offers a single-bit delay

from primary input, TDI to primary output, TDO. The device identification register contains the

device identification code.

The boundary scan register allows testing of board inter-connectivity. The boundary scan register

consists of a shift register place in series with device inputs and outputs. Using the boundary scan

patterns can be shifted in on primary input, TDI and forced onto all digital outputs.

13.15.1

TAP Controller

The TAP controller is a synchronous finite state machine clocked by the rising edge of primary

input, TCK. All state transitions are controlled using primary input, TMS. The finite state

machine is described below.

PM7347 Datasheet(PDF) 289 Page - PMC-Sierra, Inc