PM7347 datasheet(323/341 Pages) PMC

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S/UNI®-JET Data Sheet

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Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

323

Document ID: PMC-1990267, Issue 3

Notes

Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal

to the 1.4 Volt point of the output.

Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface

data bus, (D[7:0]).

A valid read cycle is defined as a logical OR of the CSB and the RDB signals.

In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR,

tHALR, tVL, tSLR, and tHLR are not applicable.

Parameter tHAR is not applicable if address latching is used.

When a set-up time is specified between an input and a clock, the set-up time is the time in

nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.

When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds

from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.

Table 49 Microprocessor Interface Write Access (Figure 76)

Symbol

Parameter

Min

Max

Units

tSAW

Address to Valid Write Set-up Time

tSDW

Data to Valid Write Set-up Time

tSALW

Address to Latch Set-up Time

tHALW

Address to Latch Hold Time

tVL

Valid Latch Pulse Width

tSLW

Latch to Write Set-up

tHLW

Latch to Write Hold

tHDW

Data to Valid Write Hold Time

tHAW

Address to Valid Write Hold Time

tVWR

Valid Write Pulse Width

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