Electronic Components Datasheet Search
  English  ▼

X  

PM7347 Datasheet(PDF) 127 Page - PMC-Sierra, Inc

Part # PM7347
Description  SATURN USER NETWORK INTERFACE for J2/E3/T3
PDF  341 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7347 Datasheet(HTML) 127 Page - PMC-Sierra, Inc

Back Button PM7347 Datasheet HTML 123Page - PMC-Sierra, Inc PM7347 Datasheet HTML 124Page - PMC-Sierra, Inc PM7347 Datasheet HTML 125Page - PMC-Sierra, Inc PM7347 Datasheet HTML 126Page - PMC-Sierra, Inc PM7347 Datasheet HTML 127Page - PMC-Sierra, Inc PM7347 Datasheet HTML 128Page - PMC-Sierra, Inc PM7347 Datasheet HTML 129Page - PMC-Sierra, Inc PM7347 Datasheet HTML 130Page - PMC-Sierra, Inc PM7347 Datasheet HTML 131Page - PMC-Sierra, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 127 / 341 page
background image
S/UNI®-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
127
Document ID: PMC-1990267, Issue 3
M3O8
The M3O8 bit controls the DS3 OOF decision criteria. When a logic one is written to M3O8,
DS3 OOF is declared when three of eight framing bits (F-bits) are in error. When a logic zero
is written to M3O8, the three of 16 framing bits in error criteria is used, as recommended in
ANSI T1.107
MBDIS
The MBDIS bit disables the use of M-bit errors as a criteria for losing frame alignment.
When MBDIS is set to logic one, M-bit errors are disabled from causing an OOF; the LOF
criteria is based solely on the number of F-bit errors selected by the M3O8 bit. When MBDIS
is set to logic zero, errors in either M-bits or F-bits are enabled to cause an OOF. When
MBDIS is logic zero, an OOF can occur when one or more M-bit errors occur in three out of
4 consecutive M-frames, or when the F-bit error ratio selected by the M3O8 bit is exceeded.
FDET
The FDET bit selects the fast detection timing for AIS, IDLE and RED. When FDET is set to
logic one, the AIS, IDLE, and RED detection time is 2.23 ms; when FDET is set to logic
zero, the detection time is 13.5 ms.
AISPAT
The AISPAT bit controls the pattern used to detect the AIS (AIS). When a logic one is written
to AISPAT, the AIS detection algorithm checks that a framed DS3 signal containing the
repeating pattern 1010.. is present. The C-bits are checked for the value specified by the AISC
bit setting. When a logic zero is written to AISPAT, the AIS detection algorithm is determined
solely by the settings of AISC and AISONES register bits (see bit mapping table in the
Additional Configuration Register description).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com