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PM7347 Datasheet(PDF) 193 Page - PMC-Sierra, Inc |
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PM7347 Datasheet(HTML) 193 Page - PMC-Sierra, Inc |
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193 / 341 page ![]() S/UNI®-JET Data Sheet Released Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 193 Document ID: PMC-1990267, Issue 3 Register 361H: RXCP-50 Configuration 2 Bit Type Function Default Bit 7 R/W CCDIS 0 Bit 6 R/W HCSPASS 0 Bit 5 R/W IDLEPASS 0 Bit 4 R/W IN52 0 Bit 3 R/W ALIGN[1] 0 Bit 2 R/W ALIGN[0] 0 Bit 1 R/W HCSFTR[1] 0 Bit 0 R/W HCSFTR[0] 0 HCSFTR[1:0] The HCS filter bits, HCSFTR[1:0] indicate the number of consecutive error-free cells required, while in detection mode, before reverting back to correction mode. Refer to Table 20. Table 20 RXCP-50 HCS Filtering Configurations HCSFTR[1:0] Cell Acceptance Threshold 00 One ATM cell with correct HCS before resumption of cell acceptance. This cell is accepted. 01 Two ATM cells with correct HCS before resumption of cell acceptance. The last cell is accepted. 10 Four ATM cells with correct HCS before resumption of cell acceptance. The last cell is accepted. 11 Eight ATM cells with correct HCS before resumption of cell acceptance. The last cell is accepted. ALIGN[1:0] ALIGN[1:0] configures the RXCP-50 to perform cell delineation based on byte, nibble, or bit wide search algorithms when ATM Direct Mapping is used. Cell alignment is relative to overhead bits in the serial input data stream. The ALIGN[1:0] bits are valid only if ATM direct mapping is used. PLCP framing must be disabled. The Recommended settings for DS3, E3, and J2 are shown in Table 21. Table 21 RXCP-50 Cell Delineation Algorithm Base ALIGN[1:0] Cell Delineation Algorithm base 00 Bit 01 Nibble (DS3) 10 Byte (E3,J2, E1, T1) 11 Unused |
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