PM7347 datasheet(195/341 Pages) PMC

195 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

195

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

R/W

RXPTYP

Bit 6

Unused

Bit 5

R/W

RCAINV

Bit 4

R/W

RCALEVEL0

Bit 3

Unused

Bit 2

Unused

Bit 1

Unused

Bit 0

R/W

FIFORST

The FIFORST bit is used to reset the four-cell receive FIFO. When FIFORST is set to logic

zero, the FIFO operates normally. When FIFORST is set to logic one, the FIFO is

immediately emptied and further writes into the FIFO are ignored (no incoming ATM cells

will be stored in the FIFO). The FIFO remains empty and continues to ignore writes until a

logic zero is written to FIFORST.

See section 12.8 on resetting the receive and transmit FIFOs.

RCALEVEL0

The RCALEVEL0 register bit selects the behavior of RCA and DRCA[x] when they de-assert

(transition to logic zero if RCAINV is logic zero, or transition to logic one if RCAINV is

logic one) as the receive FIFO empties.

When RCALEVEL0 is set to logic one, DRCA[x] and RCA indicates that the receive FIFO is

empty. RCA (and DRCA[x]), if polled, will de-assert on the rising RFCLK edge after Payload

byte 48 (ATM8=1) or Payload byte 24 (ATM8=0) is output.

When RCALEVEL0 is set to logic zero, DRCA[x] and RCA, if polled, indicates that the

receive FIFO is near empty. DRCA[x] and RCA, if polled, will de-assert on the rising

RFCLK edge after Payload byte 43 (ATM8=1) or Payload byte 19 (ATM8=0) is output.

RCAINV

The RCAINV bit inverts the polarity of the DRCA[x] and RCA output signal. When

RCAINV is a logic one, the polarity of DRCA[x] and RCA is inverted (DRCA[x] and RCA at

logic zero means there is a receive cell available to be read). When RCAINV is a logic zero,

the polarity of RCA and DRCA[x] is not inverted.

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