PM7347 datasheet(199/341 Pages) PMC

199 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

199

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

OOCDV

Bit 6

LCDV

Bit 5

Unused

Bit 4

OOCDI

Bit 3

CHCSI

Bit 2

UHCSI

Bit 1

FOVRI

Bit 0

LCDI

The LCDI bit is set high when there is a change in the loss of cell delineation (LCD) state.

This bit is reset immediately after a read to this register.

FOVRI

The FOVRI bit is set to logic one when a FIFO overrun occurs. This bit is reset immediately

after a read to this register. No further FIFO overrun indications will occur until the condition

which caused the original overrun has cleared. In the case where continuous FIFO overruns

are occurring, only a single overrun indication (FOVRI -> ‘1’) will be recorded until the

overruns cease.

UHCSI

The UHCSI bit is set high when an uncorrected HCS error is detected. This bit is reset

immediately after a read to this register.

CHCSI

The CHCSI bit is set high when a corrected HCS error is detected. This bit is reset

immediately after a read to this register.

OOCDI

The OOCDI bit is set high when the RXCP-50 enters or exits the SYNC state. The OOCDV

bit indicates whether the RXCP-50 is in the SYNC state or not. The OOCDI bit is reset

immediately after a read to this register.

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