PM8621 datasheet(119/184 Pages) PMC

119 / 184 page

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

118

Document ID: PMC-2010850, Issue 1

When multiple complete messages are being read (software knows that there is more than one

message in the FIFO using the RX_MSG_LVL bits) this bit does not need to be written

between individual message reads. It must be written for the 1st message.

When software uses a variable length message protocol it may want to abandon reading a

message buffer before reading the entire message buffer of 8 DWords (16 Words). In this case

this bit must be written with a ‘1’ to move the message pointer to the start of the next message

buffer before starting the read of that buffer.

After writing this bit with a ’1’ software should not start reading the FIFO until the

RX_FI_BUSY bit has cleared.

In the worst case this will take 5 SYSCLK cycles when FAST_RD_EN = ‘1’ and 4 SYSCLK

cycles when FAST_RD_EN = ‘0’.

At this point the 1st DWORD of the message is available for reading and the CRC_ERR bit is

valid. Software may abandon a CRC errored message without reading the message buffer by

writing this bit with a ‘1’ again.

On reads this bit is always returns the RX_SYNC_DONE status.

A suggested s/w procedure for accessing the Receive Message Buffer is outlined in section

12.12.2 (Accessing the Receive Message FIFO)

RX_SYNC_DONE

This bit indicates the status of an RX_XFER_SYNC operation. When ‘1’ it indicates that an

RX_XFER_SYNC has been done. S/W should check this bit at the start of a message read

sequence or when attempting to perform a message skip sequence.

RX_FI_BUSY

This bit indicates that the internal hardware is transferring data from the Receive FIFO RAM

into the Receive FIFO registers. The bits is set following

° A write to the Receive FIFO Synch Register (Bh) with the RX_XFER_SYNC bit set.

° A read from the Receive FIFO Data Low register.

Following an RX_XFER_SYNC write this bit need not be read by software if the time

interval to the successive Receive FIFO DATA register read is greater than approximately 5

SYSCLK cycles when FAST_RD_EN = ‘1’ or approximately 4 SYSCLK cycles when

FAST_RD_EN = ‘0’.

This bit need not be read by software if the time interval between successive Receive FIFO

DATA register reads greater than approximately 4 SYSCLK cycles when FAST_RD_EN =

‘1’ or approximately 3 SYSCLK cycles when FAST_RD_EN = ‘0’.

PM8621 Datasheet(PDF) 119 Page - PMC-Sierra, Inc