PM8621 datasheet(128/184 Pages) PMC

128 / 184 page

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

127

Document ID: PMC-2010850, Issue 1

PMCTST

The PMCTST bit is used to configure the NSE-8G for PMC's manufacturing tests. When

PMCTST is set to logic one, the NSE-8G microprocessor port becomes the test access port

used to run the PMC "canned" manufacturing test vectors. As well, the analog blocks are

placed in IDDQ mode = the digital circuitry within the analog blocks is held static The

PMCTST can be cleared by setting CSB to logic one or by writing logic zero to the bit.

PMCATST

The PMCATST bit is used to configure the analog portion of the NSE-8G for PMC's

manufacturing tests. The PMCATST bit can be cleared by setting both CSB to logic one and

RSTB to logic zero. PMCATST can also be cleared by writing logic zero to the bit.

11.2

JTAG Test Port

The NSE JTAG Test Access Port (TAP) allows access to the TAP controller and the four TAP

registers: instruction, bypass, device identification and boundary scan. Using the TAP, device

input logic levels can be read, device outputs can be forced, the device can be identified and the

device scan path can be bypassed. For more details on the JTAG port, please refer to the

Operations section.

Table 12 Instruction Register (Length - 3 bits)

Instructions

Selected Register

Instruction Codes, IR[2:0]

EXTEST

Boundary Scan

000

IDCODE

Identification

001

SAMPLE

Boundary Scan

010

BYPASS

Bypass

011

BYPASS

Bypass

100

STCTEST

Boundary Scan

101

BYPASS

Bypass

110

BYPASS

Bypass

111

Table 13 Identification Register

Length

32 bits

Version Number

Part Number – NSE-20G

8620H

Part Number – NSE–8G

8621H

Manufacturer's Identification Code

0CDH

Device Identification – NSE-20G

086200CDH

Device Identification – NSE-8G

086210CDH

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