PM8621 datasheet(143/184 Pages) PMC

143 / 184 page

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

142

Document ID: PMC-2010850, Issue 1

Figure 24 Non DS0 Switch Timing

0us

250us

500us

C1FP

SBS#1 TCMP

NSE CMP

SBS#2 OCMP

SBI Frame Time

Internal Sigs

SBS IC1FP.INT

NSE RC1FP.INT

SBS RC1FP.INT

SBS OC1FP.INT

SBS#1 TCMP.INT

NSE CMP.INT

SBS#2 OCMP.INT

12.4

NSE-8G CPU Interaction with the Switching Cycle When Using

the ILC

An interrupt is made available to the NSE-8G CPU called the Frame Interrupt this occurs at the

start of the internal frame and marks a time in the NSE-8G where updates to the system page bits

can occur. This interrupt is maskable and would normally be masked.

The CPU will need to enable this interrupt before a page switch is required, then respond to this

interrupt immediately and complete writing the new page bit settings (a two double word

operation) within 27 µs.

This is required as the ILC will sample the SBS page bits (in the ILCs) once during the frame

before the first message is assembled and sent (starting at the beginning of row 3). If the page bits

are updated late, the SBS pages will switch a frame late, which means the NSE-8G DCB may

switch early giving disastrous results.

The NSE-8G CPU will have the rest of the frame to signal a page switch to the DCB as this is

sampled on the next frame

PM8621 Datasheet(PDF) 143 Page - PMC-Sierra, Inc