PM8621 datasheet(145/184 Pages) PMC

145 / 184 page

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

144

Document ID: PMC-2010850, Issue 1

If some links are switching DS0 traffic (“1 in 48” frame mode) and some are not (“1 in 4” frame

mode), the input RC1FP and the qualifying signal from the DCB (from mf_swap), will be running

at “1 in 48” frame mode. The links in “1 in 48” frame mode should use the unexpected interrupt

while the others should use the missing interrupt.

If a link no longer has any C1 activity, the firmware should assume the link has lost alignment,

and should force R8TD OCA for the port.

These instructions assume the PMC NSE-8G Device driver is not being used. If the supplied

driver is being used, this will all be handled within that driver.

12.6

DS0 Cross-Bar Switch (DCB) Operation

While the DCB is the Space Switch central to the NSE-8G it also contains the DCB C1 Delay

RC1FP (RC1DLY) and the expected arrival time in the R8TD SIPO of the C1 character. This

value is expected to be in the order of 51 clock cycles + 9720 or +1080 for SBI mode or

TeleCombus mode respectively. The 51 value is approximate and very dependant on the system

architecture and transmission line lengths between the SBS and NSE-8G components. This must

be obtained empirically by the system designer during product commissioning.

Figure 25 Architecture of the RAM Input Interface

160

offcfg[159:0]

160

oncfg[159:0]

pgNdin[159:0]

CFGO[29:0]

12.6.1 Configuring the DCB using Port Transfer Mode

In port transfer mode, the microprocessor updates only one configuration entry within a word of

offline connection memory page. The steps to perform a port transfer are shown in the following

example:

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