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GL842 Datasheet(PDF) 11 Page - GENESYS LOGIC

Part # GL842
Description  USB 2.0 2-in-1 Scanner Controller
PDF  64 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL842 Datasheet(HTML) 11 Page - GENESYS LOGIC

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GL842 USB 2.0 2-in-1 Scanner Controller
Genesys Logic Inc.—All rights reserved.
Page 11
XPA_SW
30
O
hbd16rsc
Transparency lamp power control or CIS Green LED
array control
LED_B
31
O
hbd16rsc CIS Blue LED array control
FRONT-END Interface
Pin Name
Pin#
Type
ASIC I/O
Cell
Description
OP0~7
40~47
I
(pd)
hbd16dhk AFE digital data input
SEN/SLOAD
55
O
(pd) hbd16dhk Serial interface load pulse
SCLK
54
O
hbd16rsc Serial interface clock output
SDI
51
O
(pd)
hbd16dhk Serial data output
SDO
50
I
(pd)
hbd16dhk Serial data input
BSMP/CDSCLK1
56
O
hbd16rsc Wolfson type: Video sample synchronization pulse
Analog Device: CDS Reference level sampling clock
VSMP/CDSCLK2
57
O
hbd16rsc Wolfson type: Video sample synchronization pulse
Analog Device: CDS Data level sampling clock
MCLK/ADCCLK
58
O
hbd16rsc Wolfson type: Master clock.
Analog Device: A/D Converter sampling clock.
DRAM Interface
Pin Name
Pin#
Type
ASIC I/O
Cell
Description
DBUS0~15
95~102,
105~112
B
(pd)
hbd16dhk DRAM data bus
ABUS0~9
81,84~89,
92~94
O
(pd)
hbd16dhk DRAM address bus
RASX
78
O
(pd) hbd16dhk DRAM RAS signal of first memory chip
CASX
77
O
(pd)
hbd16dhk DRAM CAS signal of first memory chip
NOEX
79
O
(pd)
hbd16dhk DRAM OE(output enable) signal of first memory chip
NWEX
80
O
(pd) hbd16dhk DRAM WE signal of first memory chip
RASY
72
O
(pd)
hbd16dhk DRAM RAS signal of second memory chip
CASY
71
O
(pd)
hbd16dhk DRAM CAS signal of second memory chip
NOEY
73
O
(pd) hbd16dhk DRAM OE(output enable) signal of second memory chip
NWEY
76
O
(pd)
hbd16dhk DRAM WE signal of second memory chip



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