TMPR4937 datasheet(391/552 Pages) TOSHIBA

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Chapter 12 Timer/Counter

12-7

12.3.6 Watchdog Timer Mode

The Watchdog Timer mode is used to monitor system anomalies. The software periodically clears the

counter and judges an anomaly to exist if the counter is not cleared within a specified period of time.

Then, either the TX4937 is internally reset or an NMI is signaled to the TX49/H3 core. Set the Timer

mode field (TMTCR2.TMODE) of the Timer Control Register to “10” to set the timer to the Watchdog

Timer mode. This mode can only be used by Timer 2.

Use the Watchdog Reset bit (WR) of the Chip Configuration Register (CCFG) to select whether to

perform an internal reset or signal an NMI. Set this bit to “1” to select Watchdog Reset, or set it to “0”

to select NMI Signaling.

When the timer count reaches the value programmed in Compare Register A (TMCPRA2), the

Watchdog Timer TMCPRA Match Status bit in the Timer Interrupt Status Register (TMTISR2.TWIS) is

set. Either the watchdog timer reset or NMI is issued if the Timer Watchdog Enable bit in the Watchdog

Timer Mode Register (TMWTMR2.TWIE) is set.

When the watchdog timer reset is selected, the Watchdog Reset Status bit in the Chip Configuration

Setting the Watchdog Reset External Output bit (CCFG.WDREXEN) causes the WDRST* signal to be

asserted. This does not initialize the TX4937. The WDRST* signal remains asserted until the RESET*

signal is asserted. Assertion of the RESET* signal deasserts the WDRST* signal and initializes the

TX4937.

There are three ways of stopping NMI signaling from being performed.

Clear the Watchdog Timer Interrupt Status bit (TMTISR2.TWIS) of the timer Interrupt Status

Clear the counter by writing “1” to the Watchdog Timer Clear bit (TMWTMR2.TWC) of the

Watchdog Timer Mode Register.

Clear the Watchdog Timer Interrupt Enable bit (TMWTMR2.TWIE) while the Watchdog Timer

Disable bit (TMWTMR2.WDIS) is still set.

It is possible to stop the counter when in the Watchdog Timer mode by clearing the Timer Counter

Enable bit (TMTCR2.TCE) of the Timer Control Register while the Watchdog Timer Disable bit

(TMWTMR2.WDIS) of the Watchdog Timer Mode Register is set to “1”.

It is also possible to stop the counter by clearing the Counter Clock Divide Cycle Enable bit

(TMTCR2.CCDE) of the Timer Control Register when the internal clock is being used as the counter

clock.

It is not possible to directly write “0” to the Watchdog Timer Disable bit (TMWTMR2.WDIS). There

are two ways to clear this bit.

Clear the Watchdog Timer Interrupt Enable bit (TMWTMR2.WDIS)

Clear the Timer Counter Enable bit (TMTCR2.TCE) of the Timer Control Register

TMPR4937 Datasheet(PDF) 391 Page - Toshiba Semiconductor