TMPR4937 datasheet(394/552 Pages) TOSHIBA

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Chapter 12 Timer/Counter

12-10

12.4.1 Timer Control Register n (TMTCRn)

TMTCR0

0xF000

TMTCR1

0xF100

TMTCR2

0xF200

Reserved

: Type

: Initial value

Reserved

TCE

CCDE CRE Reserved ECES

CCS

TMODE

R/W

: Type

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:8

Reserved

⎯

TCE

Timer Counter

Enable

Timer Count Enable (Default: 0)

This field controls whether the counter runs or stops.

When in the Watchdog mode, counter operation only stops when the

Watchdog Timer Disable bit (TMWTMR2.WDIS) of the Watchdog Timer

Mode Register is set. When the Watchdog Timer Disable bit is cleared, the

value of this Timer Count Enable bit becomes “0”, but the count continues.

0: Stop counter (the counter is also cleared to “0” when CRE = 1)

1: Counter operation

R/W

CCDE

Counter Clock

Divider Enable

Counter Clock Divide Enable (Default: 0)

This bit enables the divide operation of the internal clock (IMBUSCLK).

The counter stops if this bit is set to “0” when the internal bus clock is in

use.

0: Disable

1: Enable

R/W

CRE

Counter Reset

Enable

Counter Reset Enable (Default: 0)

This bit controls the counter reset when the TCE bit was used to stop the

counter.

1: Stop and reset the counter to “0” when the TCE bit is cleared to “0”.

0: Only stop the counter when the TCE bit is cleared to “0”.

During CRE = 1, reset the counter if TCE is set from 1 to 0.

During TCE = 0, the counter isn’t reset if CRE is set from 0 to 1.

When TCE = 1 and CRE = 0, stop and reset the counter if TCE is set to 0

and CRE is set to 1 simultaneously.

R/W

Reserved

⎯

ECES

External Clock

Edge Select

External Clock Edge Select (Default: 0)

This bit specifies the counter operation edge when using the counter input

signal (TCLK).

0: Falling edge of the counter input signal (TCLK)

1: Rising edge of the counter input signal (TCLK)

R/W

CCS

Counter Clock

Select

Counter Clock Select (Default: 0)

This bit specifies the timer clock.

0: Internal clock (IMBUSCLK)

1: External input clock (TCLK)

R/W

1:0

TMODE

Timer Mode

Timer Mode (Default: 00)

This bit specifies the timer operation mode.

11: Reserved

10: Watchdog Timer mode (Timer 2), Reserved (Timer 0, 1)

01: Pulse Generator mode (Timer 0, 1), Reserved (Timer 2)

00: Interval Timer mode

R/W

Figure 12.4.1 Timer Control Register

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