TMPR4938 datasheet(337/716 Pages) TOSHIBA

337 / 716 page

Chapter 10 PCI Controller

10-61

10.4.33 G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE)

0xD130

Reserved

: Type

: Initial value

Reserved

BSWAP

EXFER

BA[35:32]

R/W

: Type

0x0/0x1 0x1/0x0

0x0

: Initial value

BA[31:16]

R/W

: Type

0x0000/0x1FC0

: Initial value

BA[15:8]

Reserved

R/W

: Type

0x00

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

63:38

Reserved

⎯

BSWAP

Byte Swap

Byte Swap Disable

(Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte

swapping of Memory Space 0.

1: Do not perform byte swapping.

0: Perform byte swapping.

Please use the default state in most situations. If this bit is changed to “1”

when in the Big Endian Mode, the byte order of transfer to Memory Space

0 through DWORD (32-bit) access will not change.

R/W

EXFER

Endian Transfer

(Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1)

Sets the Endian Transfer of Memory Space 0.

1: Performs Endian Transfer.

0: Does not perform Endian Transfer.

Please use the default state.

R/W

35:8

BA[35:8]

Base Address

Base Address (Default: Normal Mode: 0x0_0000_00; PCI Boot Mode:

0x0_1FC0_00)

Sets the G-Bus base bus address of Memory Space 2 for initiator access.

Can set the base address in 256-byte units.

R/W

7:0

Reserved

Figure 10.4.31 G2P Memory Space 2 G-Bus Base Address Register

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