LTM4682 datasheet(34/130 Pages) AD

34 / 130 page

LTM4682

Rev. A

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OPERATION

If an external oscillator is not provided, the SYNC_nn pins

should only be enabled on one of the LTM4682s con-

trollers. The other(s) should be programmed to disable

SYNC_nn controllers using bit 4 of MFR_CONFIG_ALL. If

an external oscillator is present, the chip with the SYNC_

nn pin enabled will detect the presence of the external

clock and disable its output.

Multiple channels need to connect all the VOSNSn+ pins

together, and all the VOSNSn– pins together, COMPna and

COMPnb pins together as well. Do not assert bit[4] of MFR_

CONFIG_ALL except in a PolyPhase application.

The user must share the SYNC_nn, SHARE_CLK_nn,

FAULTn, and ALERTn pins of these parts. Use the pull-

up resistors on SYNC_nn, FAULTn, SHARE_CLK_nn and

ALERTn. See the Typical Application section.

INTERNAL TEMPERATURE SENSE

Temperature is measured using the internal diode-con-

nected PNP transistors, and the outputs are connected to

TSNS0 to TSNS3 pins corresponding to Channels 0 to 3.

These outputs are used for testing. Two different currents

are applied to the diode (nominally 2µA and 32µA), and

the temperature is calculated from a ∆VBE measurement

made with the internal 16-bit monitor ADC (see Figure 2

Block Diagram).

The LTM4682 will only implement ∆VBE temperature sens-

ing. Therefore the MFR_PWM_MODE bit[5] is reserved.

RCONFIG (RESISTOR CONFIGURATION) PINS

There are twelve input pins utilizing 1% resistors between

these pins to select key operating parameters. The pins

are ASEL_01, ASEL_23, FSWPH_01_CFG, FSWPH_23_

CFG, VOUT0_CFG, VOUT1_CFG, VOUT2_CFG, VOUT3_

CFG, VTRIM0_CFG, VTRIM1_CFG, VTRIM2_CFG, and

VTRIM3_CFG. If pins are floated, the value stored in the

corresponding NVM command is used. If bit 6 of the

MFR_CONFIG_ALL configuration command is asserted in

NVM, the resistor input is ignored upon power-up except

for ASEL, which is always respected. The resistor con-

figuration pins are only measured during a power-up reset

or after a MFR_RESET, or after an RESTORE_USER_ALL

command is executed.

The VOUTn_CFG pin settings are described in Table 1.

These pins set the LTM4682 VOUT0 to VOUT3 output voltage

coarse settings. If the pin is open, the VOUT_COMMAND

command is loaded from NVM to determine the output

voltage. The VTRIMn_CFG pins in Table 2 are used to set

the output voltage fine adjustment setting. Both combine

to offer several distinct output voltages.

The following parameters are set as a percentage of the

output voltage if the RCONFIG pins are used to determine

the output voltage:

VOUT_OV_FAULT_LIMIT....................................+10%

VOUT_OV_WARN_LIMIT....................................+7.5%

VOUT_MAX.........................................................+7.5%

VOUT_MARGIN_HIGH........................................+5%

VOUT_MARGIN_LOW.........................................–5%

VOUT_UV_FAULT_LIMIT....................................–7%

The FSWPH_CFG_nn pin settings are described in Table 3.

This pin selects the switching frequency and phase of each

channel. The phase relationships between the two chan-

nels and the SYNC_nn pin are determined in Table 3. To

synchronize to an external clock, the part should be put

into external clock mode (SYNC_nn output disabled but

frequency set to the nominal value). If no external clock is

supplied, the part will clock at the programmed frequency.

If the application is multiphase and the SYNC_nn signal

between chips is lost, the parts will not operate at the

designed phase, even if they are programmed and trimmed

to the same frequency.

This may increase the ripple voltage on the output, possibly

producing undesirable operation. If the external SYNC_nn

signal is being generated internally and external SYNC_nn

is not selected, bit 10 of MFR_PADS will be asserted. If

no frequency is selected and the external SYNC_nn fre-

quency is not present, a PLL_FAULT will occur. If the user

does not wish to see the ALERT from a PLL_FAULT, even

if there is not a valid synchronization signal at power-up,

the ALERT mask for PLL_FAULT must be written. See the

description on SMBALERT_MASK for more details. If the

SYNC_nn pin is connected between multiple ICs, only one

of the ICs should have the SYNC_nn pin enabled using the

MFR_CONFIG_ALL[4] = 1, and all other ICs should be con-

figured to have the SYNC pin disabled with MFR_CONFIG_

ALL[4] = 0.

LTM4682 Datasheet(PDF) 34 Page - Analog Devices

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