LTM4682 datasheet(20/130 Pages) AD

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LTM4682

Rev. A

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target regulation voltage by serial bus. Its initial command

value at SVIN_01 power-up is dictated by NVM contents

(factory default: 0.75V)—or, optionally, may be set by

configuration resistors; see VOUT1_CFG, VTRIM1_CFG

and the Applications Information section.

COMP0b, COMP1b, COMP2b, COMP3b (G10, F9, T9,

W11): Current Control Threshold and Error Amplifier

Compensation Nodes. Each associated channel’s current

comparator tripping threshold increases with its compen-

sation voltage. Each channel has a 22pF to SGND.

COMP0a, COMP1a, COMP2a, COMP3a (G11, G9, T8,

V11): Loop Compensation Nodes. The internal PWM

loop compensation resistors RCOMPn of the LTM4682

can be adjusted using bit[4:0] of the MFR_PWM_COMP

command. The transconductance of the LTM4682 PWM

error amplifier can be adjusted using bit[7:5] of the MFR_

PWM_COMP command. These two loop compensation

parameters can be programmed when the device is in

operation. See the Programmable Loop Compensation

subsection in the Applications Information section for

further details. See Figure 1.

PGOOD0, PGOOD1, PGOOD2, PGOOD3 (H9, H8, R10,

T10): Power Good Indicator Outputs. The open-drain logic

output is pulled to the ground when the output exceeds

the UV and OV regulation window. The output is de-

glitched by an internal 100µs filter. A pull-up resistor to

3.3V is required in the application.

IIN_01+ (H10): Positive Current Sense Amplifier Input.

If the input current sense amplifier is not used, this pin

must be shorted to the IIN_01– and SVIN_01 pin. See the

Applications Information section for more details about

the input current sensing.

VOSNS0– (H11): Channel 0 Negative Differential Voltage

Sense Input. See VOSNS0+.

SVIN_01 (J8): Input Supply for LTM4682’s Internal Control

IC for Channels 0 and 1. In most applications, SVIN_01

connects to VIN01. SVIN_01 can be operated from an aux-

iliary supply separate from VIN01 for powering the VIN01

from a lower supply like 6V. The SVIN_01 pin requires

1Ω and 1µF decoupling capacitor to measure the actual

control chip current. The 1Ω resistor is used to measure

the actual control chip current. See MFR_READ_ICHIP

and MFR_ADC_CONTROL COMMAND section. When

operating from 4.5V to 5.75V with no auxiliary bias sup-

ply, then the main input supply should connect to SVIN_01

and INTVCC_01. See Test Circuit 2 for an example. In this

configuration, the ICHIP current will not be relevant since

INTVCC_01 is connected to SVIN_01.

INTVCC_01 (J9): Internal Regulator, 5.5V Output. When

operating the LTM4682 from 5.75V ≤ SVIN_01 ≤ 16V, an

internal LDO generates INTVCC_01 from SVIN_01 to bias

internal control circuits and the MOSFET drivers of the

LTM4682’s Channels 0 and 1. An external 4.7µF ceramic

decoupling capacitor is required. The INTVCC_01 is on

regulated regardless of the RUNn pin state. When operat-

ing the LTM4682 with 4.5V ≤ SVIN_01 < 5.75V, INTVCC_01

must be electrically shorted to SVIN_01, and the RUNP pin

must be pulled to GND. The VBIAS takes over after startup

when the input voltage is greater than 7V.

IIN_01– (J10): Negative Current Sense Amplifier Input. If

the input current sense amplifier is not used, this pin

must be shorted to the IIN_01+ and SVIN_01 pin. See the

Applications Information section for more details about

the input current sensing.

VOSNS0+ (J11): Channel 0 Positive Differential Voltage

Sense Input. Together, VOSNS0+ and VOSNS0– serve to

Kelvin-sense the VOUT0 output voltage at VOUT0’s point

of load (POL) and provide the differential feedback signal

directly to Channel 0’s feedback loop. Command VOUT0’s

target regulation voltage by serial bus. Its initial command

value at SVIN_01 power-up is dictated by NVM contents

(factory default: 0.75V)—or, optionally, may be set by

configuration resistors; see VOUT0_CFG, VTRIM0_CFG

and the Applications Information section.

VIN23 (N5-N6, P5-P6, R5-R6, T5-T6, U5-U6, V5-V6,

W5-W6, Y5-Y6, AA5-AA6, AB5-AB6): Positive Power

Input to Channels 2 and 3 Switching Stages. Provide suf-

ficient decoupling capacitance in the form of MLCCs and

low ESR electrolytic (or equivalent) to handle reflected

input current ripple from the step-down switching stage.

The MLCCs should be placed as close to the LTM4682

as physically possible. See the Layout Checklist/Example

section in the Applications Information section.

PIN FUNCTIONS

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