LTM4682 datasheet(29/130 Pages) AD

29 / 130 page

LTM4682

Rev. A

For more information www.analog.com

OPERATION

from a CRC issue is not recommended. All power sup-

ply rails associated with either PWM channel of a device

reporting an invalid CRC should remain disabled until the

issue is resolved. See the Applications Information sec-

tion or contact the factory for more details on efficient in-

system EEPROM programming, including bulk EEPROM

Programming, which the LTM4682 also supports.

The LTM4682 contains two dual internal constant fre-

quency current mode control buck regulators (Channel 0

and Channel 1, and Channel 2 and Channel 3) and whose

power MOSFETs are capable of fast switching speed.

Reference to the signal pins will be Name_nn, where n is

either 01 or 23, or with namen when referring to signal pins

that are related to the actual channel. The factory NVM-

default switching frequency clocks SYNC_nn at 575kHz, to

which the regulators synchronize their switching frequency.

The default phase-interleaving angle between the channels

is 180°. A pin-strapping resistor on FSWPH_nn_CFG con-

figures the frequency of the SYNC_nn clock (switching

frequency) and the channel phase relationship of the chan-

nels to each other and for the falling edge of the SYNC_nn

signal. (Most possible combinations of the switching fre-

quency and the phase-angle assignments are settleable

by the resistor pin programming; see Table 3. Configure

the LTM4682’s NVM to implement settings unavailable

by resistor-pin strapping.) When a FSWPH_nn_CFG pin-

strap resistor sets the channel phase relationship of the

LTM4682’s channels, the SYNC_nn clock is not driven by

the module. Instead, SYNC_nn becomes strictly a high

impedance input, and the channel switching frequency is

then synchronized to SYNC_nn provided by an externally-

generated clock or sibling LTM4682 with a pull-up resistor

to VDD33_nn. Switching frequency and phase relationship

can be altered through the I2C interface, but only when the

switching action is off, i.e., when the module is not regulat-

ing the outputs. See the Applications Information section

for more details.

Programmable analog feedback loop compensation for

Channel 0 to Channel 3 is accomplished with a capaci-

tor connection from COMPna to SGND, and a capacitor

from COMPnb to SGND.) The COMPnb pin is for the

high frequency gain roll-off and is the gm amplifier out-

put that has a programmable range, and the COMPna

pin has the programmable resistor range, along with a

capacitor to SGND that sets the frequency compensa-

tion. See the Programmable Loop Compensation section.

The LTM4682 module has sufficient stability margins and

good transient performance with a wide range of output

capacitors—even all-ceramic MLCCs. Table 13 provides

guidance on input and output capacitors recommended

for many common operating conditions, along with

the programmable compensation settings. The Analog

Devices LTpowerCAD® tool is available for transient and

stability analysis, and experienced users who prefer to

adjust the module’s feedback loop compensation param-

eters can use this tool.

POWER-UP AND INITIALIZATION

The LTM4682 is designed to provide standalone supply

sequencing and controlled turn-on and turn-off operation.

It operates from a single input supply (4.5V to 16V) while

three on-chip linear regulators generate internal 2.5V,

3.3V, and 5.5V per controller. If the VINnn does not exceed

5.75V, and the VBIAS pin is turned off, the INTVCC, VINnn

and SVIN_nn pins must be connected together. The con-

troller configuration is initialized by an internal threshold-

based UVLO where VINnn must be approximately 4V, and

the 5.5V, 3.3V, and 2.5V linear regulators must be within

approximately 20% of the regulated values. In addition

to the power supply, a PMBus RESTORE_USER_ALL or

MFR_RESET command can initialize the part, too.

The VBIAS pin is the output of an internal 5.5V buck regula-

tor to improve the efficiency of the circuit and minimize

power loss on the LTM4682. The VBIAS pin must exceed

approximately 4.8V, and VIN must exceed 7V before the

INTVCC LDO operates from the VBIAS pin. The VBIAS regu-

lator is powered from VIN_VBIAS and enabled with RUNP.

During initialization, the external configuration resistors

are identified and/or contents of the NVM are read into the

controller’s commands, and the power train is held off. The

RUNn, FAULTn, and PGOODn are held low. The LTM4682

will use the contents of Table 1 through Table 5 to determine

the resistor-defined parameters. See the RCONFIG (Resistor

Configuration) Pins section for more details. The resistor

configuration pins only control some of the preset values

of the controller. The remaining values are programmed in

NVM either at the factory or by the user.

LTM4682 Datasheet(PDF) 29 Page - Analog Devices

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