LTM4682 datasheet(67/130 Pages) AD

67 / 130 page

LTM4682

Rev. A

For more information www.analog.com

APPLICATIONS INFORMATION

command. An example polling loop is shown in Figure 33,

which ensures that commands are processed in order

while simplifying error-handling routines.

When the part receives a new command while it is busy,

it will communicate this condition using standard PMBus

protocol. Depending on the part configuration it may

either NACK the command or return all ones (0xFF) for

reads. It may also generate a BUSY fault and ALERT noti-

fication, or stretch the SCL clock low. For more informa-

tion, refer to PMBus Specification v1.1, Part II, Section

10.8.7, and SMBus v2.0, section 4.3.3. Clock stretching

can be enabled by asserting bit 1 of MFR_CONFIG_ALL.

Clock stretching will only occur if enabled, and the bus

communication speed exceeds 100kHz.

// wait until chip is not busy

{

mfrCommonValue = PMBUS_READ_BYTE(0xEF);

partReady = (mfrCommonValue & 0x68) == 0x68;

}while(!partReady)

// now the part is ready to receive the next

command

PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_

COMMAND to 2V

Figure 33. Example of a Command Write of VOUT_COMMAND

The PMBus busy protocols are well-accepted standards,

but can make writing system-level software somewhat

complex. The part provides three hand-shaking status

bits, which reduce complexity while enabling robust sys-

tem-level communication.

The three hand-shaking status bits are in the MFR_

COMMON register. When the part is busy executing an

internal operation, it will clear bit 6 of MFR_COMMON

(chip not busy). When the part is busy specifically because

it is in a transitional VOUT state (margining hi/lo, power

off/on, moving to a new output voltage set point, etc.), it

will clear bit 4 of MFR_COMMON (output not in transi-

tion). When internal calculations are in process, the part

will clear bit 5 of MFR_COMMON (calculations not pend-

ing). These three status bits can be polled with a PMBus

read byte of the MFR_COMMON register until all three bits

are set. A command immediately following the status bits

being set will be accepted without NACKing or generat-

ing a BUSY fault/ALERT notification. The part can NACK

commands for other reasons, however, as required by the

PMBus spec (for instance, an invalid command or data).

An example of a robust command write algorithm for the

VOUT_COMMAND register is provided in Figure 33.

It is recommended that all command writes (write byte,

write word, etc.) be preceded with a polling loop to avoid

the extra complexity of dealing with busy behavior and

unwanted ALERT notifications. A simple way to achieve

this is to create a SAFE_WRITE_BYTE() and SAFE_

WRITE_WORD() subroutine. The above polling mecha-

nism allows your software to remain clean and simple

while robustly communicating with the part. For a detailed

discussion of these topics and other special cases,

refer to the Application Note search section feature at

Analog.com.

When communicating using bus speeds at or below

100kHz, the polling mechanism shown here provides a

simple solution that ensures robust communication with-

out clock stretching. At bus speeds in excess of 100kHz,

it is strongly recommended that the part be configured

to enable clock stretching. This requires a PMBus main

device that supports clock stretching. System software

that detects and properly recovers from the standard

PMBus NACK/BUSY faults as described in the PMBus

Specification v1.1, Par II, Section 10.8.7 is required to

communicate. The LTM4682 is not recommended in

applications with bus speeds in excess of 400kHz.

THERMAL CONSIDERATIONS AND OUTPUT

CURRENT DERATING

The thermal resistances reported in the Pin Configuration

section of this data sheet are consistent with those param-

eters defined by JESD51-12. They are intended for use

with finite element analysis (FEA) software modeling

tools that leverage the outcome of thermal modeling,

simulation, and correlation to hardware evaluation per-

formed on a µModule package mounted to a hardware

test board defined by JESD51-9 (Test Boards for Area

Array Surface Mount Package Thermal Measurements).

The motivation for providing these thermal coefficients is

found in JESD51-12 (Guidelines for Reporting and Using

Electronic Package Thermal Information).

LTM4682 Datasheet(PDF) 67 Page - Analog Devices

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