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LTM4682 Datasheet(PDF) 23 Page - Analog Devices |
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LTM4682 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 130 page  23 LTM4682 Rev. A For more information www.analog.com SIMPLIFIED BLOCK DIAGRAM Figure 2. Simplified LTM4682 Block Diagram of the 1/2 Function DECOUPLING REQUIREMENTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CINH External High Frequency Input Capacitor Requirement (5.75V ≤ VIN ≤ 16V, VOUTn Commanded to 0.75V). IOUT0 = 31.25A IOUT1 = 31.25A 100 100 µF µF COUTn External High Frequency Output Capacitor Requirement (5.75V ≤ VIN ≤ 16V, VOUTn Commanded to 0.75V). IOUT0 = 31.25A IOUT1 = 31.25A 800 800 µF µF 4682 F02 IOUT CURRENT SENSE IOUT CURRENT SENSE 0.22µF MT MB MT MB 4.7µF RSENSE CIN2 CIN1 120nH 2.2µF 2.2µF 120nH 0.01µF 0.01µF COUT1 COUT2 COUT3 COUT4 CLOAD CLOAD 22pF CCOMPL CCOMPH PROG GM 22pF PROG RCOMP CCOMPL CCOMPH 2.2µF 14.3k EACH PIN INTVCC_01, INTVCC_23 INPUT CURRENT/ICHIP (READ_IIN, MFR_READ_IIN_PEAK TO ANALOG READBACK) VIN01, VIN23 SW0, SW2 SW1, SW3 VOUT1 VIN VOUT0 TSNS1 TSNS0 GND GND SGND_01, SGND_23 TSNS1, TSNS3 TSNS0, TSNS2 X1 VOSNS0+, VOSNS2+ VOSNS0–, VOSNS2– REMOTE SENSE REMOTE SENSE VOSNS1+, VOSNS3+ VOSNS1–, VOSNS3– VOUT1, VOUT3 ADJ TO 1.35V UP TO 31.25A COMP0b, COMP2b COMP0a, COMP2a COMP1b, COMP3b COMP1a, COMP3a PGOOD0, PGOOD2 PGOOD1, PGOOD3 SPI SUBORDINATE SPI MAIN POWER CONTROL DIGITAL SECTION SYNC_01, SYNC_23 VDD25_01, VDD25_23 VTRIM0_CFG VTRIM1_CFG VOUT0_CFG VOUT1_CFG FSWPH_01_CFG, FSWPH_23_CFG 2.5V DIGITAL ENGINE 3.3V TOLERANT PULL-UP NOT SHOWN EXTERNAL RESISTIVE DIVIDERS BETWEEN VDD25_nn AND SGND_nn ARE NOT SHOWN. REFER TO TABLES 1, 2 AND 3. ASEL_01, ASEL_23 POWER CONTROL ANALOG SECTION VOUT2_CFG, VOUT3_CFG VTRIM2_CFG, VTRIM3_CFG + – EA1,3 – + X1 VIN_VBIAS RUNP EEPROM ROM RAM 32MHz OSC SYNC DRIVER + – EA0,2 PROG RCOMP PROG GM ADC 10:1 MUX DIE TEMP SENSE TEMP MUX VOUT0, VOUT2 ADJ TO 1.35V UP TO 31.25A LOAD – + A = N 1µF 22µF 0.1µF 2.2µF 0.22µF VDD33_01, VDD33_23 VBIAS VBIAS SVIN_01, SVIN_23 IN_01–, IN_23– IN_01+, IN_23+ VIN01, VIN23 1 + ALL ANALOG READBACK SIGNALS TO ANALOG READBACK TO ANALOG READBACK LOAD 5.5V VIN ALL PINS SHOWN IS FUNCTION ×2 TO SUPPORT CHANNELS 0 AND 1, AND CHANNELS 2 AND 3. TWO DIFFERENT PSM CONTROLLERS 1ST CONTROLLER (PAGE 0X00) = CHANNEL 0 (PAGE 0X01) = CHANNEL 1 2ND CONTROLLER (PAGE 0X00) = CHANNEL 2 (PAGE 0X01) = CHANNEL 3 SVIN_01, SVIN_23 > 7V SCL_01, SCL_23 SDA_01, SDA_23 ALERT_01, ALERT_23 WP_01, WP_23 RUN0, RUN1 RUN2, RUN3 FAULT0, FAULT1 FAULT2, FAULT3 SHARE_CLK_01, SHARE_CLK_23 3.3V-TOLERANT, PULL-UP RESISTORS NOT SHOWN 5V-TOLERANT, PULL-UP RESISTORS NOT SHOWN 5V-TOLERANT, PULL-UP RESISTORS NOT SHOWN 3.3V-TOLERANT, PULL-UP RESISTORS NOT SHOWN CHANNEL# GUI IDENTITY 0 1 2 3 U0:A0 U0:A1 U0:B0 U0:B1 TA = 25°C. Using Figure 2 configuration. |
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