ISM330BXTR datasheet(100/150 Pages) STMICROELECTRONICS

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11.3

EMB_FUNC_EN_B (05h)

Enable embedded functions register (R/W)

Table 191. EMB_FUNC_EN_B register

0(1)

MLC_EN

FIFO_

COMPR_EN

0(1)

FSM_EN

1. This bit must be set to 0 for the correct operation of the device.

Table 192. EMB_FUNC_EN_B register description

MLC_EN(1)

Enables machine learning core function. When the machine learning core is enabled by setting this bit

to 1, the MLC algorithms are executed after the FSM programs. Default value: 0

(0: machine learning core function disabled;

1: machine learning core function enabled and executed after FSM programs)

FIFO_COMPR_EN(2)

Enables FIFO compression function. Default value: 0

(0: FIFO compression function disabled;

1: FIFO compression function enabled)

FSM_EN

Enables finite state machine (FSM) function. Default value: 0

(0: FSM function disabled; 1: FSM function enabled)

1. MLC_BEFORE_FSM_EN bit in the EMB_FUNC_EN_A (04h) register must be set to 0 when using this bit.

2. This bit is active when the FIFO_COMPR_RT_EN bit of FIFO_CTRL2 (08h) is set to 1.

11.4

EMB_FUNC_EXEC_STATUS (07h)

Embedded functions execution status register (R)

Table 193. EMB_FUNC_EXEC_STATUS register

EMB_FUNC_

EXEC_OVR

EMB_FUNC

_ENDOP

Table 194. EMB_FUNC_EXEC_STATUS register description

EMB_FUNC_EXEC_OVR

This bit is set to 1 when the execution of the embedded functions program exceeds maximum time

(new data are generated before the end of the algorithms). Default value: 0

EMB_FUNC_ENDOP

When this bit is set to 1, no embedded function is running. Default value: 0

ISM330BX

Embedded functions register description

DS14588 - Rev 2

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