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ISM330BXTR Datasheet(PDF) 33 Page - STMicroelectronics |
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ISM330BXTR Datasheet(HTML) 33 Page - STMicroelectronics |
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33 / 150 page  5.3.4 TDM configurations All the ISM330BX TDM configurations programmable through the I²C/SPI/I3C interface are detailed in the following subsections. 5.3.4.1 Configuration 1 • No delay: SLOT0 data MSB is sampled on the first rising edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CFG0 (6Ch) bit 6 equal to zero) • Data valid: data valid on the rising edge of BCLK (data_valid I²C register TDM_CFG0 (6Ch) bit 5 equal to zero) Figure 17. WCLK, TDMout change on the falling edge of BCLK and are valid on the rising edge of BCLK, no delay Note: Setup and hold times are defined in Table 9. TDM timing values. 5.3.4.2 Configuration 2 • No delay: SLOT0 data MSB is sampled on the first falling edge of BCLK after rising edge of WCLK (delayed I²C register TDM_CFG0 (6Ch) bit 6 equal to zero) • Data valid: data valid on the falling edge of BCLK (data_valid I²C register TDM_CFG0 (6Ch) bit 5 equal to one) Figure 18. WCLK, TDMout change on the rising edge of BCLK and are valid on the falling edge of BCLK, no delay Note: Setup and hold times are defined in Table 9. TDM timing values. ISM330BX Digital interfaces DS14588 - Rev 2 page 33/150 |
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