PCM5121 datasheet(103/121 Pages) TI2

103 / 121 page

103

PCM5121, PCM5122

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SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018

Product Folder Links: PCM5121 PCM5122

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12.1.1.4

Page 44 Registers

Table 128. Page 44 / Register 1

Dec

Hex

RSV

ACRM

AMDC

ACRS

ACSW

Reset Value

RSV

Reserved

Reserved. Do not access.

ACRM

Active CRAM Monitor (Read Only)

This bit indicates which CRAM is being accessed by the DSP when adaptive mode is disabled. When adaptive

mode is enabled, this bit has no meaning.

0: CRAM A is being used by the DSP

1: CRAM B is being used by the DSP

AMDC

Adaptive Mode Control

This bit controls the DSP adaptive mode. When in adaptive mode, only CRAM A is accessible via serial

interface when the DSP is disabled (DAC in standby state), while when the DSP is enabled (DAC is run state)

the CRAM A can only be accessed by the DSP and the CRAM B can only be accessed by the serial interface,

or vice versa depending on the value of CRAMSTAT. When not in adaptive mode, both CRAM A and B can be

accessed by the serial interface when the DSP is disabled, but when the DSP is enabled, no CRAM can be

accessed by serial interface. The DSP can access either CRAM, which can be monitored at SWPMON.

Default value: 0

0: Adaptive mode disabled

1: Adaptive mode enabled

ACRS

Active CRAM Selection (Read Only)

This bit indicates which CRAM currently serves as the active one. The other CRAM serves as an update buffer,

and can accessed by serial interface (SPI/I2C)

0: CRAM A is active and being used by the DSP

1: CRAM B is active and being used by the DSP

ACSW

Switch Active CRAM

This bit is used to request switching roles of the two buffers, that is, switching the active buffer role between

CRAM A and CRAM B. This bit is cleared automatically when the switching process completed.

Default value: 0

0: No switching requested or switching completed

1: Switching is being requested

12.1.1.5

Page 253 Registers

Table 129. Page 253 / Register 63

Dec

Hex

PLLFLEX1

Reset Value

PLLFLEX1[7:0]

Clock Flex Register #1

Clock Flex Register #1. Write 0x11 to this register to allow advanced clock tree functions. See Clocking

Overview section.

Default value: 00000000

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