AM625 datasheet(156/276 Pages) TI2

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6.12.5.11.2 GPMC and NOR Flash — Asynchronous Mode

Table 6-67 and Table 6-68 present timing requirements and switching characteristics for GPMC and NOR Flash

— Asynchronous Mode.

Table 6-67. GPMC and NOR Flash Timing Requirements – Asynchronous Mode

see Figure 6-51, Figure 6-52, Figure 6-53, and Figure 6-55

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

FA5(1)

tacc(d)

Data access time

H(5)

FA20(2) tacc1-pgmode(d)

Page mode successive data access time

P(4)

FA21(3) tacc2-pgmode(d)

Page mode first data access time

H(5)

(1)

The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active

functional clock edge. FA5 value must be stored inside the AccessTime register bit field.

(2)

The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of

GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional

clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3)

The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

(4)

P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(5)

H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(6)

GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

Table 6-68. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode

see Figure 6-51, Figure 6-52, Figure 6-53, Figure 6-54, Figure 6-55, and Figure 6-56

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

FA0

tw(be[x]nV)

Pulse duration, output lower-byte enable and command latch enable

GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid

time

N(12)

FA1

tw(csnV)

Pulse duration, output chip select GPMC_CSn[i](13) low

A(1)

FA3

td(csnV-advnIV)

Delay time, output chip select GPMC_CSn[i](13) valid to output

address valid and address latch enable GPMC_ADVn_ALE invalid

B(2) - 2

B(2) + 2

FA4

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13) valid to output

enable GPMC_OEn_REn invalid (Single read)

C(3) - 2

C(3) + 2

FA9

td(aV-csnV)

Delay time, output address GPMC_A[27:1] valid to output chip

select GPMC_CSn[i](13) valid

J(9) - 2

J(9) + 2

FA10

td(be[x]nV-csnV)

Delay time, output lower-byte enable and command latch enable

GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to

output chip select GPMC_CSn[i](13) valid

J(9) - 2

J(9) + 2

FA12

td(csnV-advnV)

Delay time, output chip select GPMC_CSn[i](13) valid to output

address valid and address latch enable GPMC_ADVn_ALE valid

K(10) - 2

K(10) + 2

FA13

td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](13) valid to output

enable GPMC_OEn_REn valid

L(11) - 2

L(11) + 2

FA16

tw(aIV)

Pulse duration output address GPMC_A[26:1] invalid between 2

successive read and write accesses

G(7)

FA18

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13) valid to output

enable GPMC_OEn_REn invalid (Burst read)

I(8) - 2

I(8) + 2

FA20

tw(aV)

Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and

4th accesses

D(4)

FA25

td(csnV-wenV)

Delay time, output chip select GPMC_CSn[i](13) valid to output write

enable GPMC_WEn valid

E(5) - 2

E(5) + 2

FA27

td(csnV-wenIV)

Delay time, output chip select GPMC_CSn[i](13) valid to output write

enable GPMC_WEn invalid

F(6) - 2

F(6) + 2

FA28

td(wenV-dV)

Delay time, output write enable GPMC_WEn valid to output data

GPMC_AD[15:0] valid

AM625, AM625-Q1, AM623, AM620-Q1

SPRSP58C – JUNE 2022 – REVISED OCTOBER 2025

www.ti.com

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