AM625 datasheet(152/276 Pages) TI2

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Multiplexed mode: data transition at WRDATAONADMUXBUS × (TimeParaGranularity + 1) × GPMC_FCLK(15)

(10) Case CLK DIV 1 mode, all data and byte enables after initial transfer: Data and byte enables transition on fall edge of GPMC_CLK

(Half cycle of GPMC_CLK)

(11) Case modes other than CLK DIV 1 mode (GPMC_CLK divided down from GPMC_FCLK): All data and byte enables transition on

fall edge of GPMC_CLK (Half cycle of GPMC_CLK). ClkActivationTime, GPMCFCLKDIVIDER, RDACCESSTIME/WRACCESSTIME,

and PAGEBURSTACCESSTIME configuration must be configured to enforce data and byte enables transition on falling edge of

GPMC_CLK (to be latched on rise edge of GPMC_CLK)

(12) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

(13) P = GPMC_CLK period in ns

(14) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)

For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(15)

(15) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(16) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the

GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.

GPMC_CLK

GPMC_CSn[i]

GPMC_A[MSB:1]

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADVn_ALE

GPMC_OEn_REn

GPMC_AD[15:0]

GPMC_WAIT[j]

Valid Address

D 0

F12

F13

F11

F19

F18

F20

F10

F19

F12

GPMC_01

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-46. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)

AM625, AM625-Q1, AM623, AM620-Q1

SPRSP58C – JUNE 2022 – REVISED OCTOBER 2025

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