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6.12.5.11 GPMC

For more details about features and additional description information on the device General-Purpose Memory

Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Table 6-64 presents timing conditions for GPMC.

Table 6-64. GPMC Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

1.65

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

133MHz Synchronous Mode

140

360

All other modes

140

720

td(Trace Mismatch

Delay)

Propagation delay mismatch across all traces

200

For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the

device TRM.

6.12.5.11.1 GPMC and NOR Flash — Synchronous Mode

Table 6-65 and Table 6-66 present timing requirements and switching characteristics for GPMC and NOR Flash -

Synchronous Mode.

Table 6-65. GPMC and NOR Flash Timing Requirements — Synchronous Mode

see Figure 6-46, Figure 6-47, and Figure 6-50

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

F12

tsu(dV-clkH)

Setup time, GPMC_AD[15:0] valid before GPMC_CLK

high

0.92

F13

th(clkH-dV)

Hold time, GPMC_AD[15:0] valid after GPMC_CLK high

2.09

F21

tsu(waitV-clkH)

Setup time, GPMC_WAIT[j](1) (2) valid before GPMC_CLK

high

0.92

F22

th(clkH-waitV)

Hold time, GPMC_WAIT[j](1) (2) valid after GPMC_CLK

high

2.09

(1)

In GPMC_WAIT[j], j is equal to 0 or 1.

(2)

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-

Purpose Memory Controller (GPMC) section in the device TRM.

Table 6-66. GPMC and NOR Flash Switching Characteristics – Synchronous Mode

see Figure 6-46, Figure 6-47, Figure 6-48, Figure 6-49, and Figure 6-50

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tc(clk)

Cycle time, GPMC_CLK(16)

7.52

tw(clkH)

Typical pulse duration, GPMC_CLK high

0.475P(13) -

0.3

tw(clkL)

Typical pulse duration, GPMC_CLK low

0.475P(13) -

0.3

td(clkH-csnV)

Delay time, GPMC_CLK rising edge to GPMC_CSn[i]

transition(12)

F(5) - 2.2

F(5) + 3.75

td(clkH-CSn[i]V)

Delay time, GPMC_CLK rising edge to GPMC_CSn[i]

invalid(12)

D(4) - 2.2

D(4) + 4.5

td(aV-clk)

Delay time, GPMC_A[27:1] valid to GPMC_CLK first edge

B(2) - 2.3

B(2) + 4.5

td(clkH-aIV)

Delay time, GPMC_CLK rising edge to GPMC_A[27:1] invalid

-2.3

4.5

AM625, AM625-Q1, AM623, AM620-Q1

SPRSP58C – JUNE 2022 – REVISED OCTOBER 2025

www.ti.com

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