RF6001 datasheet(35/70 Pages) RFMD

35 / 70 page

35 of 70

RF6001

Rev A3 DS050929

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Part of the POLARIS™ TOTAL RADIO™ Solution

Case 4: GMSK FIFO Clocking Signals Generated by Baseband, TXD_MODE=1, TXF=10

The FIFO will automatically clear under three conditions: 1) if the SDI reset field is programmed; 2) at the end of any transmis-

sion burst following the end of the ramp down; and, 3) if the SDI field FCLR is set. This will clear the contents of the FIFO mem-

ory and designate the next bit written as the first output bit of the FIFO. The baseband will then generate a clock of less than or

equal to 26MHz applied to MCK. On every rising edge of MCK, the baseband will assert an NRZ data bit on MDI if TXCKINV is

low. The RF6001 will read this data if MS is high on every falling edge of MCK if TXCKINV is set low. If TXCKINV is set high then

the baseband will assert an NRZ data bit on the falling edge of MCK and the RF6001 will read this data bit if MS is high on

every rising edge of MCK. This data will be stored in a FIFO register of length 1024 bits in the RF6001. The diagram below sum-

marizes this part of the interface. This is the same as Case 5 except that the data is framed by MS.

Transmission is initiated by setting the TXST or TXEN pins to a logical high. If TX_ST is set high then an internal timer, TXENU, is

programmed to delay the rise of TX_EN. A second timer, MD_DLY, determines when the modulation stored in the FIFO will begin

to be output relative to the rising edge of TX_ST. Data will be output at a 13MHz/48 rate. New data CAN be loaded into the

FIFO input while the output is active. The second diagram below summarizes the operation of the second step of this interface.

TXCKINV=0, TXF=10

MDI

FIFO

Count

MCK

Auto Clear

CWH

CWL

TXCKINV=1, TXF=10

Auto Clear

MCK

FIFO

Count

MDI

RF6001 Datasheet(PDF) 35 Page - RF Micro Devices