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RF6001
Rev A3 DS050929
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Part of the POLARIS™ TOTAL RADIO™ Solution
SSI - Address 110001
Location
Bit Name
Default
Function
SSI(17:16)
CLKRM(1:0)
00
CLKR Mode
0=CLKR is enabled when ENR=1, but operates only during the active data portion of
the transfer (disabled during any blank data portion).
01=CLKR is enabled when ENR=1 and remains on regardless of the state of DBL.
1x=CLKR is always disabled.
SSI(15)
RXCKB
0
Receive Clock Source
0=CLKR is an output
1=CLKR is an input
SSI(14)
RXFSB
0
Receive Frame Sync Source
0=FSR is an output
1=FSR is an input
SSI(13)
FS_LOC
0
Frame Sync Location
0=FSR coincident with MSB of I data
1=FSR occurs on clock before MSB of I data
SSI(12)
EN_SEL
0
Receive SSI Mode
0=RXSSI starts with ENR
1=RXSSI starts with RXEN
SSI(11)
RX_T
0
RXSSI Trailing Clock Pulses. Adds clocks to the end of an RXSSI transfer.
0=No extra clock cycles are added to the end of an RXSSR transfer.
1=5 extra clock cycles are added to the end of an RXSSR transfer.
SSI(10)
CLKRINV
0
Inverts the CLKR signal.
0=Uninverted, normal polarity
1=Inverted polarity
SSI(9)
TXD_MODE
0
TX Digital Interface Mode
0=Digital TX interface, MCK and MS are outputs
1=Digital TX interface, MCK and MS are inputs
SSI(8:7)
TXF(1:0)
00
Controls the FIFO Interface Modes
00=TX FIFO disabled
01=No MS mode. FIFO will shift in bits on every falling edge of MCK, regardless of the
MS signal.
10=MS FRAME mode. FIFO will shift in bits on every falling edge of MCK, if MS is high.
11=MS PULSE mode. At every MS pulse, the FIFO will shift in a predetermined number
of bits. The position of MS, relative to the first data bit is controlled by MS_LOC. The
number of bits shifted in is determined by MS_LEN[4:0].
SSI(6)
TXCKINV
0
TX Clock Invert
0=Data is latched on the falling edge of MCK
1=Data is latched on the rising edge of MCK
SSI(5)
INTNEN
0
Test bit. Program to 0.
SSI(4:1)
MS_LEN(3:0)
0
MS Pulse Length. In TXF=11 mode, MS_LEN controls the number of bits the TX FIFO will
shift in, on every MS pulse.
MS_LEN=0: 4 bits
MS_LEN=6: 10 bits
MS_LEN=12: 24 bits
MS_LEN=1: 5 bits
MS_LEN=7: 11 bits
MS_LEN=13: 26 bits
MS_LEN=2: 6 bits
MS_LEN=8: 12 bits
MS_LEN=14: 32 bits
MS_LEN=3: 7 bits
MS_LEN=9: 13 bits
MS_LEN=15: 48 bits
MS_LEN=4: 8 bits
MS_LEN=10: 14 bits
MS_LEN=5: 9 bits
MS_LEN=11: 16 bits
SSI(0)
MS_LOC
0
MS Pulse Location
0=transfer of first data bit occurs on same clock period as the pulse on MS
1=transfer of first data bit occurs on the next clock period after the pulse on MS
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